Implement Log
Created on 0:53:18 17.07.2013
InputFile = E:/prog/pcie_ds_dma/trunk/projects/sp605_lx45t_core/implement/xie0.ini
File 'E:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_core\src\top\sp605_lx45t_core.ucf' has been copied to 'E:/prog/pcie_ds_dma/trunk/projects/sp605_lx45t_core/implement/ver1/rev1/sp605_lx45t_core.ucf'
Executing "C:\Xilinx\14.5\ISE_DS\ISE\bin\nt\ngdbuild.exe" -p 6SLX45TFGG484-3 -aul -sd "E:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_core\src\adm\coregen" -sd "E:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_core\src\pcie_src\components\coregen" -sd "E:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_core\synthesis" -sd "E:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_core\compile" -sd "E:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_core\src" -uc "sp605_lx45t_core.ucf" "sp605_lx45t_core.ngc" "sp605_lx45t_core.ngd"
Release 14.5 - ngdbuild P.58f (nt)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Command Line: C:\Xilinx\14.5\ISE_DS\ISE\bin\nt\unwrapped\ngdbuild.exe -p
6SLX45TFGG484-3 -aul -sd
E:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_core\src\adm\coregen -sd
E:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_core\src\pcie_src\components\core
gen -sd E:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_core\synthesis -sd
E:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_core\compile -sd
E:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_core\src -uc sp605_lx45t_core.ucf
sp605_lx45t_core.ngc sp605_lx45t_core.ngd
Reading NGO file
"E:/prog/pcie_ds_dma/trunk/projects/sp605_lx45t_core/implement/ver1/rev1/sp605_l
x45t_core.ngc" ...
Loading design module
"E:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_core\src\pcie_src\components\cor
egen/ctrl_fifo64x34fw.ngc"...
Loading design module
"E:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_core\src\pcie_src\components\cor
egen/ctrl_fifo64x37st.ngc"...
Executing edif2ngd -noa -aul
"E:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_core\src\adm\coregen\ctrl_mux8x1
6r.edn" "ctrl_mux8x16r.ngo"
Release 14.5 - edif2ngd P.58f (nt)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
INFO:NgdBuild - Release 14.5 edif2ngd P.58f (nt)
INFO:NgdBuild - Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Writing module to "ctrl_mux8x16r.ngo"...
Loading design module
"E:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_core\implement\ver1\rev1\ctrl_mu
x8x16r.ngo"...
Executing edif2ngd -noa -aul
"E:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_core\src\adm\coregen\ctrl_mux16x
16.edn" "ctrl_mux16x16.ngo"
Release 14.5 - edif2ngd P.58f (nt)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
INFO:NgdBuild - Release 14.5 edif2ngd P.58f (nt)
INFO:NgdBuild - Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Writing module to "ctrl_mux16x16.ngo"...
Loading design module
"E:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_core\implement\ver1\rev1\ctrl_mu
x16x16.ngo"...
Executing edif2ngd -noa -aul
"E:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_core\src\adm\coregen\ctrl_mux8x4
8.edn" "ctrl_mux8x48.ngo"
Release 14.5 - edif2ngd P.58f (nt)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
INFO:NgdBuild - Release 14.5 edif2ngd P.58f (nt)
INFO:NgdBuild - Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Writing module to "ctrl_mux8x48.ngo"...
Loading design module
"E:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_core\implement\ver1\rev1\ctrl_mu
x8x48.ngo"...
Executing edif2ngd -noa -aul
"E:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_core\src\adm\coregen\ctrl_fifo10
24x65_v5.edn" "ctrl_fifo1024x65_v5.ngo"
Release 14.5 - edif2ngd P.58f (nt)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
INFO:NgdBuild - Release 14.5 edif2ngd P.58f (nt)
INFO:NgdBuild - Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Writing module to "ctrl_fifo1024x65_v5.ngo"...
Loading design module
"E:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_core\implement\ver1\rev1\ctrl_fi
fo1024x65_v5.ngo"...
Loading design module
"E:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_core\src\adm\coregen/ctrl_fifo10
24x65_v5_fifo_generator_v3_2_xst_1.ngc"...
Loading design module
"E:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_core\src\adm\coregen/ctrl_multip
lier_v1_0.ngc"...
Gathering constraint information from source properties...
Done.
Annotating constraints to design from ucf file "sp605_lx45t_core.ucf" ...
NgdBuild - The value of SIM_DEVICE on instance
'amb/gen_syn.pcie/core/ep/pcie_bram_top/pcie_brams_rx/brams[3].ram/ramb16' of
type RAMB16BWER has been changed from 'SPARTAN3ADSP' to 'SPARTAN6' to correct
post-ngdbuild and timing simulation for this primitive. In order for
functional simulation to be correct, the value of SIM_DEVICE should be
changed in this same manner in the source netlist or constraint file.
NgdBuild - The value of SIM_DEVICE on instance
'amb/gen_syn.pcie/core/ep/pcie_bram_top/pcie_brams_rx/brams[2].ram/ramb16' of
type RAMB16BWER has been changed from 'SPARTAN3ADSP' to 'SPARTAN6' to correct
post-ngdbuild and timing simulation for this primitive. In order for
functional simulation to be correct, the value of SIM_DEVICE should be
changed in this same manner in the source netlist or constraint file.
NgdBuild - The value of SIM_DEVICE on instance
'amb/gen_syn.pcie/core/ep/pcie_bram_top/pcie_brams_rx/brams[1].ram/ramb16' of
type RAMB16BWER has been changed from 'SPARTAN3ADSP' to 'SPARTAN6' to correct
post-ngdbuild and timing simulation for this primitive. In order for
functional simulation to be correct, the value of SIM_DEVICE should be
changed in this same manner in the source netlist or constraint file.
NgdBuild - The value of SIM_DEVICE on instance
'amb/gen_syn.pcie/core/ep/pcie_bram_top/pcie_brams_rx/brams[0].ram/ramb16' of
type RAMB16BWER has been changed from 'SPARTAN3ADSP' to 'SPARTAN6' to correct
post-ngdbuild and timing simulation for this primitive. In order for
functional simulation to be correct, the value of SIM_DEVICE should be
changed in this same manner in the source netlist or constraint file.
NgdBuild - The value of SIM_DEVICE on instance
'amb/gen_syn.pcie/core/ep/pcie_bram_top/pcie_brams_tx/brams[3].ram/ramb16' of
type RAMB16BWER has been changed from 'SPARTAN3ADSP' to 'SPARTAN6' to correct
post-ngdbuild and timing simulation for this primitive. In order for
functional simulation to be correct, the value of SIM_DEVICE should be
changed in this same manner in the source netlist or constraint file.
NgdBuild - The value of SIM_DEVICE on instance
'amb/gen_syn.pcie/core/ep/pcie_bram_top/pcie_brams_tx/brams[2].ram/ramb16' of
type RAMB16BWER has been changed from 'SPARTAN3ADSP' to 'SPARTAN6' to correct
post-ngdbuild and timing simulation for this primitive. In order for
functional simulation to be correct, the value of SIM_DEVICE should be
changed in this same manner in the source netlist or constraint file.
NgdBuild - The value of SIM_DEVICE on instance
'amb/gen_syn.pcie/core/ep/pcie_bram_top/pcie_brams_tx/brams[1].ram/ramb16' of
type RAMB16BWER has been changed from 'SPARTAN3ADSP' to 'SPARTAN6' to correct
post-ngdbuild and timing simulation for this primitive. In order for
functional simulation to be correct, the value of SIM_DEVICE should be
changed in this same manner in the source netlist or constraint file.
NgdBuild - The value of SIM_DEVICE on instance
'amb/gen_syn.pcie/core/ep/pcie_bram_top/pcie_brams_tx/brams[0].ram/ramb16' of
type RAMB16BWER has been changed from 'SPARTAN3ADSP' to 'SPARTAN6' to correct
post-ngdbuild and timing simulation for this primitive. In order for
functional simulation to be correct, the value of SIM_DEVICE should be
changed in this same manner in the source netlist or constraint file.
NgdBuild - The value of SIM_DEVICE on instance
'dio_out/x_fifo/ctrl_fifo/BU2/U0/gen_as.fgas/normgen.memblk/bmem.bmg.bmg_inst
/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2.ram/dp18x18.ram/RAMB16BWER'
of type RAMB16BWER has been changed from 'SPARTAN3ADSP' to 'SPARTAN6' to
correct post-ngdbuild and timing simulation for this primitive. In order for
functional simulation to be correct, the value of SIM_DEVICE should be
changed in this same manner in the source netlist or constraint file.
NgdBuild - The value of SIM_DEVICE on instance
'dio_out/x_fifo/ctrl_fifo/BU2/U0/gen_as.fgas/normgen.memblk/bmem.bmg.bmg_inst
/blk_mem_generator/valid.cstr/ramloop[1].ram.r/v2.ram/dp18x18.ram/RAMB16BWER'
of type RAMB16BWER has been changed from 'SPARTAN3ADSP' to 'SPARTAN6' to
correct post-ngdbuild and timing simulation for this primitive. In order for
functional simulation to be correct, the value of SIM_DEVICE should be
changed in this same manner in the source netlist or constraint file.
NgdBuild - The value of SIM_DEVICE on instance
'dio_out/x_fifo/ctrl_fifo/BU2/U0/gen_as.fgas/normgen.memblk/bmem.bmg.bmg_inst
/blk_mem_generator/valid.cstr/ramloop[2].ram.r/v2.ram/dp18x18.ram/RAMB16BWER'
of type RAMB16BWER has been changed from 'SPARTAN3ADSP' to 'SPARTAN6' to
correct post-ngdbuild and timing simulation for this primitive. In order for
functional simulation to be correct, the value of SIM_DEVICE should be
changed in this same manner in the source netlist or constraint file.
NgdBuild - The value of SIM_DEVICE on instance
'dio_out/x_fifo/ctrl_fifo/BU2/U0/gen_as.fgas/normgen.memblk/bmem.bmg.bmg_inst
/blk_mem_generator/valid.cstr/ramloop[3].ram.r/v2.ram/dp18x18.ram/RAMB16BWER'
of type RAMB16BWER has been changed from 'SPARTAN3ADSP' to 'SPARTAN6' to
correct post-ngdbuild and timing simulation for this primitive. In order for
functional simulation to be correct, the value of SIM_DEVICE should be
changed in this same manner in the source netlist or constraint file.
NgdBuild - The value of SIM_DEVICE on instance
'dio_in/x_fifo/ctrl_fifo/BU2/U0/gen_as.fgas/normgen.memblk/bmem.bmg.bmg_inst/
blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2.ram/dp18x18.ram/RAMB16BWER'
of type RAMB16BWER has been changed from 'SPARTAN3ADSP' to 'SPARTAN6' to
correct post-ngdbuild and timing simulation for this primitive. In order for
functional simulation to be correct, the value of SIM_DEVICE should be
changed in this same manner in the source netlist or constraint file.
NgdBuild - The value of SIM_DEVICE on instance
'dio_in/x_fifo/ctrl_fifo/BU2/U0/gen_as.fgas/normgen.memblk/bmem.bmg.bmg_inst/
blk_mem_generator/valid.cstr/ramloop[1].ram.r/v2.ram/dp18x18.ram/RAMB16BWER'
of type RAMB16BWER has been changed from 'SPARTAN3ADSP' to 'SPARTAN6' to
correct post-ngdbuild and timing simulation for this primitive. In order for
functional simulation to be correct, the value of SIM_DEVICE should be
changed in this same manner in the source netlist or constraint file.
NgdBuild - The value of SIM_DEVICE on instance
'dio_in/x_fifo/ctrl_fifo/BU2/U0/gen_as.fgas/normgen.memblk/bmem.bmg.bmg_inst/
blk_mem_generator/valid.cstr/ramloop[2].ram.r/v2.ram/dp18x18.ram/RAMB16BWER'
of type RAMB16BWER has been changed from 'SPARTAN3ADSP' to 'SPARTAN6' to
correct post-ngdbuild and timing simulation for this primitive. In order for
functional simulation to be correct, the value of SIM_DEVICE should be
changed in this same manner in the source netlist or constraint file.
NgdBuild - The value of SIM_DEVICE on instance
'dio_in/x_fifo/ctrl_fifo/BU2/U0/gen_as.fgas/normgen.memblk/bmem.bmg.bmg_inst/
blk_mem_generator/valid.cstr/ramloop[3].ram.r/v2.ram/dp18x18.ram/RAMB16BWER'
of type RAMB16BWER has been changed from 'SPARTAN3ADSP' to 'SPARTAN6' to
correct post-ngdbuild and timing simulation for this primitive. In order for
functional simulation to be correct, the value of SIM_DEVICE should be
changed in this same manner in the source netlist or constraint file.
Resolving constraint associations...
Checking Constraint Associations...
INFO:ConstraintSystem:59 - Constraint <INST
cl_s6pcie_m2_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i LOC =
GTPA1_DUAL_X0Y1;> [sp605_lx45t_core.ucf(111)]: INST
"cl_s6pcie_m2_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i" not found.
Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
ConstraintSystem - A target design object for the Locate constraint
'<INST cl_s6pcie_m2_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i LOC =
GTPA1_DUAL_X0Y1;> [sp605_lx45t_core.ucf(111)]' could not be found and so the
Locate constraint will be removed.
ConstraintSystem:119 - Constraint <NET sys_reset_n TIG;>
[sp605_lx45t_core.ucf(134)]: This constraint cannot be distributed from the
design objects matching 'NET "sys_reset_n"' because those design objects do
not contain or drive any instances of the correct type.
ConstraintSystem - Constraint <NET sys_clk_p TNM_NET = GT_REFCLK_OUT;>
[sp605_lx45t_core.ucf(141)] was not distributed to the output pin
GTPCLKOUT0<0> of block gtpa1_dual_i because the signal path to this output
pin depends upon block attribute settings. Constraint distribution does not
support attribute dependent distribution.
INFO:ConstraintSystem:178 - TNM 'GT_REFCLK_OUT', used in period specification
'TS_GT_REFCLK_OUT', was traced into BUFIO2 instance gt_refclk_bufio2. The
following new TNM groups and period specifications were generated at the
BUFIO2 output(s):
DIVCLK: <TIMESPEC TS_amb_gen_syn_pcie_core_ep_gt_refclk_buf = PERIOD
"amb_gen_syn_pcie_core_ep_gt_refclk_buf" TS_GT_REFCLK_OUT HIGH 50%>
INFO:ConstraintSystem:178 - TNM 'amb_gen_syn_pcie_core_ep_gt_refclk_buf', used
in period specification 'TS_amb_gen_syn_pcie_core_ep_gt_refclk_buf', was
traced into PLL_ADV instance PLL_ADV. The following new TNM groups and period
specifications were generated at the PLL_ADV output(s):
CLKOUT1: <TIMESPEC TS_amb_gen_syn_pcie_core_ep_clk_125 = PERIOD
"amb_gen_syn_pcie_core_ep_clk_125" TS_amb_gen_syn_pcie_core_ep_gt_refclk_buf
HIGH 50%>
INFO:ConstraintSystem:178 - TNM 'amb_gen_syn_pcie_core_ep_gt_refclk_buf', used
in period specification 'TS_amb_gen_syn_pcie_core_ep_gt_refclk_buf', was
traced into PLL_ADV instance PLL_ADV. The following new TNM groups and period
specifications were generated at the PLL_ADV output(s):
CLKOUT0: <TIMESPEC TS_amb_gen_syn_pcie_core_ep_clk_250 = PERIOD
"amb_gen_syn_pcie_core_ep_clk_250" TS_amb_gen_syn_pcie_core_ep_gt_refclk_buf
/ 2 HIGH 50%>
INFO:ConstraintSystem:178 - TNM 'amb_gen_syn_pcie_core_ep_gt_refclk_buf', used
in period specification 'TS_amb_gen_syn_pcie_core_ep_gt_refclk_buf', was
traced into PLL_ADV instance PLL_ADV. The following new TNM groups and period
specifications were generated at the PLL_ADV output(s):
CLKOUT2: <TIMESPEC TS_amb_gen_syn_pcie_core_ep_clk_62_5 = PERIOD
"amb_gen_syn_pcie_core_ep_clk_62_5" TS_amb_gen_syn_pcie_core_ep_gt_refclk_buf
/ 0.5 HIGH 50%>
Done...
Checking expanded design ...
NgdBuild:452 - logical net
'dio_in/x_fifo/ctrl_fifo/BU2/prog_empty_thresh<0>' has no driver
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 479
Writing NGD file "sp605_lx45t_core.ngd" ...
Total REAL time to NGDBUILD completion: 19 sec
Total CPU time to NGDBUILD completion: 10 sec
Writing NGDBUILD log file "sp605_lx45t_core.bld"...
NGDBUILD done.
Executing "C:\Xilinx\14.5\ISE_DS\ISE\bin\nt\map.exe" -p 6SLX45TFGG484-3 -o "map.ncd" -pr b -ol high -ignore_keep_hierarchy -ir off -t 1 -xt 0 -r 4 -global_opt off -lc auto -power off -mt off "sp605_lx45t_core.ngd" "sp605_lx45t_core.pcf"
Release 14.5 - Map P.58f (nt)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Using target part "6slx45tfgg484-3".
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:54 - 'xc6slx45t' is a WebPack part.
Security:42 - Your software subscription period has lapsed. Your current
Xilinx software updates or new releases.
----------------------------------------------------------------------
Mapping design into LUTs...
Writing file map.ngm...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 25 secs
Total CPU time at the beginning of Placer: 20 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:bf8892b0) REAL time: 29 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:bf8892b0) REAL time: 29 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:f8ab0290) REAL time: 29 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:ece01499) REAL time: 47 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:ece01499) REAL time: 47 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:ece01499) REAL time: 47 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:ece01499) REAL time: 47 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:ece01499) REAL time: 47 secs
Phase 9.8 Global Placement
..
......
........
.........
........
......
..
.......
.......
.......
.
.
........
....
......
........
........
........
.....
....
.
........
.......
.........
........
........
.
........
........
.
.........
.....
.
.......
........
........
........
.....
..
........
.....
.....
..
........
......
....
.
.......
.
........
.......
..
.
........
.......
.
........
........
........
........
.
....
.....
.........
.........
........
........
........
.........
........
...
.
...........
.............
...........
Phase 9.8 Global Placement (Checksum:f62dfdf2) REAL time: 2 mins
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:f62dfdf2) REAL time: 2 mins
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:d6fee090) REAL time: 2 mins 16 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:d6fee090) REAL time: 2 mins 16 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:638abcb7) REAL time: 2 mins 16 secs
Total REAL time to Placer completion: 2 mins 17 secs
Total CPU time to Placer completion: 2 mins 11 secs
Running post-placement packing...
Writing output files...
Design Summary:
Number of errors: 0
Number of warnings: 43
Slice Logic Utilization:
Number of Slice Registers: 4,527 out of 54,576 8%
Number used as Flip Flops: 4,526
Number used as Latches: 1
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 4,105 out of 27,288 15%
Number used as logic: 3,147 out of 27,288 11%
Number using O6 output only: 1,799
Number using O5 output only: 570
Number using O5 and O6: 778
Number used as ROM: 0
Number used as Memory: 470 out of 6,408 7%
Number used as Dual Port RAM: 388
Number using O6 output only: 222
Number using O5 output only: 12
Number using O5 and O6: 154
Number used as Single Port RAM: 60
Number using O6 output only: 35
Number using O5 output only: 10
Number using O5 and O6: 15
Number used as Shift Register: 22
Number using O6 output only: 17
Number using O5 output only: 1
Number using O5 and O6: 4
Number used exclusively as route-thrus: 488
Number with same-slice register load: 439
Number with same-slice carry load: 49
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 1,504 out of 6,822 22%
Number of MUXCYs used: 1,132 out of 13,644 8%
Number of LUT Flip Flop pairs used: 4,981
Number with an unused Flip Flop: 1,336 out of 4,981 26%
Number with an unused LUT: 876 out of 4,981 17%
Number of fully used LUT-FF pairs: 2,769 out of 4,981 55%
Number of unique control sets: 229
Number of slice register sites lost
to control set restrictions: 854 out of 54,576 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 5 out of 296 1%
Number of LOCed IOBs: 5 out of 5 100%
Number of bonded IPADs: 4 out of 16 25%
Number of LOCed IPADs: 2 out of 4 50%
Number of bonded OPADs: 2 out of 8 25%
Number of LOCed OPADs: 2 out of 2 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 28 out of 116 24%
Number of RAMB8BWERs: 0 out of 232 0%
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
Number used as BUFIO2s: 1
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 4 out of 16 25%
Number used as BUFGs: 4
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 8 0%
Number of ILOGIC2/ISERDES2s: 0 out of 376 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 376 0%
Number of OLOGIC2/OSERDES2s: 0 out of 376 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 256 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 58 0%
Number of GTPA1_DUALs: 1 out of 2 50%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCIE_A1s: 1 out of 1 100%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 1 out of 4 25%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.18
Peak Memory Usage: 389 MB
Total REAL time to MAP completion: 2 mins 23 secs
Total CPU time to MAP completion: 2 mins 16 secs
Mapping completed.
See MAP report file "map.mrp" for details.
Executing "C:\Xilinx\14.5\ISE_DS\ISE\bin\nt\par.exe" -w -ol high -p -mt off map.ncd "sp605_lx45t_core.ncd" "sp605_lx45t_core.pcf"
Release 14.5 - par P.58f (nt)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Constraints file: sp605_lx45t_core.pcf.
Loading device for application Rf_Device from file '6slx45t.nph' in environment C:\Xilinx\14.5\ISE_DS\ISE\.
"sp605_lx45t_core" is an NCD, version 3.2, device xc6slx45t, package fgg484, speed -3
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:54 - 'xc6slx45t' is a WebPack part.
Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue
to function, but you no longer qualify for Xilinx software updates or new releases.
----------------------------------------------------------------------
Par:381 - One or more of the following switches -p and -r is not supported for this architecture. PAR will
ignore the switch and processing will continue
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
Device speed data version: "PRODUCTION 1.23 2013-03-26".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 4,527 out of 54,576 8%
Number used as Flip Flops: 4,526
Number used as Latches: 1
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 4,105 out of 27,288 15%
Number used as logic: 3,147 out of 27,288 11%
Number using O6 output only: 1,799
Number using O5 output only: 570
Number using O5 and O6: 778
Number used as ROM: 0
Number used as Memory: 470 out of 6,408 7%
Number used as Dual Port RAM: 388
Number using O6 output only: 222
Number using O5 output only: 12
Number using O5 and O6: 154
Number used as Single Port RAM: 60
Number using O6 output only: 35
Number using O5 output only: 10
Number using O5 and O6: 15
Number used as Shift Register: 22
Number using O6 output only: 17
Number using O5 output only: 1
Number using O5 and O6: 4
Number used exclusively as route-thrus: 488
Number with same-slice register load: 439
Number with same-slice carry load: 49
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 1,504 out of 6,822 22%
Number of MUXCYs used: 1,132 out of 13,644 8%
Number of LUT Flip Flop pairs used: 4,981
Number with an unused Flip Flop: 1,336 out of 4,981 26%
Number with an unused LUT: 876 out of 4,981 17%
Number of fully used LUT-FF pairs: 2,769 out of 4,981 55%
Number of slice register sites lost
to control set restrictions: 0 out of 54,576 0%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 5 out of 296 1%
Number of LOCed IOBs: 5 out of 5 100%
Number of bonded IPADs: 4 out of 16 25%
Number of LOCed IPADs: 2 out of 4 50%
Number of bonded OPADs: 2 out of 8 25%
Number of LOCed OPADs: 2 out of 2 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 28 out of 116 24%
Number of RAMB8BWERs: 0 out of 232 0%
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
Number used as BUFIO2s: 1
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 4 out of 16 25%
Number used as BUFGs: 4
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 8 0%
Number of ILOGIC2/ISERDES2s: 0 out of 376 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 376 0%
Number of OLOGIC2/OSERDES2s: 0 out of 376 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 256 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 58 0%
Number of GTPA1_DUALs: 1 out of 2 50%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCIE_A1s: 1 out of 1 100%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 1 out of 4 25%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Overall effort level (-ol): High
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 10 secs
Finished initial Timing Analysis. REAL time: 10 secs
Par:288 - The signal
amb/gen_syn.pcie/core/rx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM9_RAMD_O has no load.
PAR will not attempt to route this signal.
Par:288 - The signal
amb/gen_syn.pcie/core/rx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMD_O has no load.
PAR will not attempt to route this signal.
Par:288 - The signal
amb/gen_syn.pcie/core/rx/fifo1_cmpl/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM9_RAMD_O has no load.
PAR will not attempt to route this signal.
Par:288 - The signal
amb/gen_syn.pcie/core/rx/fifo1_cmpl/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMD_O has no load.
PAR will not attempt to route this signal.
Par:288 - The signal
amb/gen_syn.pcie/core/rx/fifo1_cmpl/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMD_O has no load.
PAR will not attempt to route this signal.
Par:288 - The signal
amb/gen_syn.pcie/core/rx/fifo1_cmpl/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM10_RAMD_O has no load.
PAR will not attempt to route this signal.
Par:288 - The signal
amb/gen_syn.pcie/core/rx/fifo1_cmpl/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMD_O has no load.
PAR will not attempt to route this signal.
Par:288 - The signal
amb/gen_syn.pcie/core/rx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM12_RAMA_DPO has no
load. PAR will not attempt to route this signal.
Par:288 - The signal
amb/gen_syn.pcie/core/rx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM12_RAMB_DPO has no
load. PAR will not attempt to route this signal.
Par:288 - The signal
amb/gen_syn.pcie/core/rx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM12_RAMD_O has no load.
PAR will not attempt to route this signal.
Par:288 - The signal
amb/gen_syn.pcie/core/rx/fifo1_cmpl/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM12_RAMB_DPO has no
load. PAR will not attempt to route this signal.
Par:288 - The signal
amb/gen_syn.pcie/core/rx/fifo1_cmpl/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM12_RAMC_DPO has no
load. PAR will not attempt to route this signal.
Par:288 - The signal
amb/gen_syn.pcie/core/rx/fifo1_cmpl/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM12_RAMD_O has no load.
PAR will not attempt to route this signal.
Par:288 - The signal
amb/gen_syn.pcie/core/rx/fifo1_cmpl/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM11_RAMC_DPO has no
load. PAR will not attempt to route this signal.
Par:288 - The signal
amb/gen_syn.pcie/core/rx/fifo1_cmpl/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM11_RAMD_O has no load.
PAR will not attempt to route this signal.
Par:288 - The signal
amb/gen_syn.pcie/core/rx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMD_O has no load.
PAR will not attempt to route this signal.
Par:288 - The signal
amb/gen_syn.pcie/core/rx/fifo1_cmpl/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMD_O has no load.
PAR will not attempt to route this signal.
Par:288 - The signal
amb/gen_syn.pcie/core/rx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMD_O has no load.
PAR will not attempt to route this signal.
Par:288 - The signal
amb/gen_syn.pcie/core/rx/fifo1_cmpl/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMD_O has no load.
PAR will not attempt to route this signal.
Par:288 - The signal
amb/gen_syn.pcie/core/rx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMD_O has no load.
PAR will not attempt to route this signal.
Par:288 - The signal
amb/gen_syn.pcie/core/rx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMD_O has no load.
PAR will not attempt to route this signal.
Par:288 - The signal
amb/gen_syn.pcie/core/rx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM10_RAMD_O has no load.
PAR will not attempt to route this signal.
Par:288 - The signal
amb/gen_syn.pcie/core/rx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMD_O has no load.
PAR will not attempt to route this signal.
Par:288 - The signal
amb/gen_syn.pcie/core/rx/fifo1_cmpl/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMD_O has no load.
PAR will not attempt to route this signal.
Par:288 - The signal
amb/gen_syn.pcie/core/rx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM8_RAMD_O has no load.
PAR will not attempt to route this signal.
Par:288 - The signal
amb/gen_syn.pcie/core/rx/fifo1_cmpl/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM8_RAMD_O has no load.
PAR will not attempt to route this signal.
Par:288 - The signal
amb/gen_syn.pcie/core/rx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM11_RAMC_DPO has no
load. PAR will not attempt to route this signal.
Par:288 - The signal
amb/gen_syn.pcie/core/rx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM11_RAMD_O has no load.
PAR will not attempt to route this signal.
Par:288 - The signal
amb/gen_syn.pcie/core/rx/fifo1_cmpl/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMD_O has no load.
PAR will not attempt to route this signal.
Par:288 - The signal
amb/gen_syn.pcie/core/rx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMD_O has no load.
PAR will not attempt to route this signal.
Par:288 - The signal
amb/gen_syn.pcie/core/tx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMD_O has no load.
PAR will not attempt to route this signal.
Par:288 - The signal
amb/gen_syn.pcie/core/tx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMD_O has no load.
PAR will not attempt to route this signal.
Par:288 - The signal
amb/gen_syn.pcie/core/tx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM9_RAMD_O has no load.
PAR will not attempt to route this signal.
Par:288 - The signal
amb/gen_syn.pcie/core/tx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM10_RAMD_O has no load.
PAR will not attempt to route this signal.
Par:288 - The signal
amb/gen_syn.pcie/core/tx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMD_O has no load.
PAR will not attempt to route this signal.
Par:288 - The signal
amb/gen_syn.pcie/core/tx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM11_RAMD_O has no load.
PAR will not attempt to route this signal.
Par:288 - The signal
amb/gen_syn.pcie/core/tx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM8_RAMD_O has no load.
PAR will not attempt to route this signal.
Par:288 - The signal
amb/gen_syn.pcie/core/tx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMD_O has no load.
PAR will not attempt to route this signal.
Par:288 - The signal
amb/gen_syn.pcie/core/tx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMD_O has no load.
PAR will not attempt to route this signal.
Par:288 - The signal
amb/gen_syn.pcie/core/tx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMD_O has no load.
PAR will not attempt to route this signal.
Par:288 - The signal
amb/gen_syn.pcie/core/tx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMD_O has no load.
PAR will not attempt to route this signal.
Starting Router
Phase 1 : 24762 unrouted; REAL time: 12 secs
Phase 2 : 19596 unrouted; REAL time: 14 secs
Phase 3 : 6823 unrouted; REAL time: 33 secs
Phase 4 : 6823 unrouted; (Setup:0, Hold:9960, Component Switching Limit:0) REAL time: 36 secs
Updating file: sp605_lx45t_core.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:10346, Component Switching Limit:0) REAL time: 52 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:10346, Component Switching Limit:0) REAL time: 52 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:10346, Component Switching Limit:0) REAL time: 52 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:10346, Component Switching Limit:0) REAL time: 52 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 53 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 55 secs
Total REAL time to Router completion: 55 secs
Total CPU time to Router completion: 55 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| clk | BUFGMUX_X3Y13| No | 1311 | 0.055 | 1.276 |
+---------------------+--------------+------+------+------------+-------------+
| clk200 | BUFGMUX_X2Y3| No | 66 | 0.015 | 1.248 |
+---------------------+--------------+------+------+------------+-------------+
|amb/gen_syn.pcie/cor | | | | | |
| e/ep/mgt_clk | BUFGMUX_X2Y2| No | 3 | 0.082 | 1.311 |
+---------------------+--------------+------+------+------------+-------------+
|amb/gen_syn.pcie/cor | | | | | |
| e/ep/mgt_clk_2x | BUFGMUX_X2Y4| No | 2 | 0.009 | 1.311 |
+---------------------+--------------+------+------+------------+-------------+
|main/d_test0/reset_r | | | | | |
|eg_test_mode_AND_577 | | | | | |
| _o | Local| | 2 | 0.000 | 0.474 |
+---------------------+--------------+------+------+------------+-------------+
| amb/clk30k | Local| | 2 | 0.000 | 2.812 |
+---------------------+--------------+------+------+------------+-------------+
|amb/gen_syn.blink/cn | | | | | |
| t30k<12> | Local| | 3 | 0.000 | 0.474 |
+---------------------+--------------+------+------+------------+-------------+
|amb/gen_syn.refclk_i | | | | | |
| buf_ML_IBUF2 | Local| | 1 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|amb/gen_syn.refclk_i | | | | | |
| buf_ML_IBUF1 | Local| | 1 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
| amb/mgt125 | Local| | 1 | 0.000 | 0.001 |
+---------------------+--------------+------+------+------------+-------------+
|amb/gen_syn.blink/cn | | | | | |
| t30k_0 | Local| | 2 | 0.000 | 0.447 |
+---------------------+--------------+------+------+------------+-------------+
|amb/gen_syn.blink/cn | | | | | |
| t30k<9> | Local| | 2 | 0.000 | 0.287 |
+---------------------+--------------+------+------+------------+-------------+
|amb/gen_syn.blink/cn | | | | | |
| t30k<10> | Local| | 2 | 0.000 | 0.312 |
+---------------------+--------------+------+------+------------+-------------+
|amb/gen_syn.blink/cn | | | | | |
| t30k<11> | Local| | 2 | 0.000 | 0.498 |
+---------------------+--------------+------+------+------------+-------------+
|amb/gen_syn.blink/cn | | | | | |
| t30k<1> | Local| | 2 | 0.000 | 0.607 |
+---------------------+--------------+------+------+------------+-------------+
|amb/gen_syn.blink/cn | | | | | |
| t30k<2> | Local| | 2 | 0.000 | 0.312 |
+---------------------+--------------+------+------+------------+-------------+
|amb/gen_syn.blink/cn | | | | | |
| t30k<3> | Local| | 2 | 0.000 | 0.475 |
+---------------------+--------------+------+------+------------+-------------+
|amb/gen_syn.blink/cn | | | | | |
| t30k<4> | Local| | 2 | 0.000 | 0.494 |
+---------------------+--------------+------+------+------------+-------------+
|amb/gen_syn.blink/cn | | | | | |
| t30k<5> | Local| | 2 | 0.000 | 0.447 |
+---------------------+--------------+------+------+------------+-------------+
|amb/gen_syn.blink/cn | | | | | |
| t30k<6> | Local| | 2 | 0.000 | 0.658 |
+---------------------+--------------+------+------+------------+-------------+
|amb/gen_syn.blink/cn | | | | | |
| t30k<7> | Local| | 2 | 0.000 | 0.475 |
+---------------------+--------------+------+------+------------+-------------+
|amb/gen_syn.blink/cn | | | | | |
| t30k<8> | Local| | 2 | 0.000 | 0.494 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
Number of Timing Constraints that were not applied: 3
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_amb_gen_syn_pcie_core_ep_clk_125 = PER | SETUP | 4.126ns| 3.874ns| 0| 0
IOD TIMEGRP "amb_gen_syn_pcie_cor | HOLD | 0.244ns| | 0| 0
e_ep_clk_125" TS_amb_gen_syn_pcie | MINPERIOD | 0.000ns| 8.000ns| 0| 0
_core_ep_gt_refclk_buf HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_amb_gen_syn_pcie_core_ep_clk_62_5 = PE | SETUP | 5.271ns| 10.729ns| 0| 0
RIOD TIMEGRP "amb_gen_syn_pcie_co | HOLD | 0.137ns| | 0| 0
re_ep_clk_62_5" TS_amb_gen_syn_pc | MINPERIOD | 0.000ns| 16.000ns| 0| 0
ie_core_ep_gt_refclk_buf / 0.5 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_amb_gen_syn_pcie_core_ep_clk_250 = PER | MINPERIOD | 0.875ns| 3.125ns| 0| 0
IOD TIMEGRP "amb_gen_syn_pcie_cor | | | | |
e_ep_clk_250" TS_amb_gen_syn_pcie | | | | |
_core_ep_gt_refclk_buf / 2 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_amb_gen_syn_pcie_core_ep_gt_refclk_buf | MINLOWPULSE | 4.666ns| 3.334ns| 0| 0
= PERIOD TIMEGRP "amb_gen_syn_pc | | | | |
ie_core_ep_gt_refclk_buf" TS_GT_REFCLK_OU | | | | |
T HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_GT_REFCLK_OUT = PERIOD TIMEGRP "GT_REF | MINPERIOD | 4.875ns| 3.125ns| 0| 0
CLK_OUT" 8 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_TO_maind_test0reg_1_LDC = MAXDELAY TO | MAXDELAY | 12.000ns| 4.000ns| 0| 0
TIMEGRP "TO_maind_test0reg_1_LDC" | HOLD | 1.405ns| | 0| 0
TS_amb_gen_syn_pcie_core_ep_clk_62_5 DAT | | | | |
APATHONLY | | | | |
----------------------------------------------------------------------------------------------------------
Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for TS_GT_REFCLK_OUT
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_GT_REFCLK_OUT | 8.000ns| 3.125ns| 8.000ns| 0| 0| 0| 105917|
| TS_amb_gen_syn_pcie_core_ep_gt| 8.000ns| 3.334ns| 8.000ns| 0| 0| 0| 105917|
| _refclk_buf | | | | | | | |
| TS_amb_gen_syn_pcie_core_ep_c| 8.000ns| 8.000ns| N/A| 0| 0| 45| 0|
| lk_125 | | | | | | | |
| TS_amb_gen_syn_pcie_core_ep_c| 4.000ns| 3.125ns| N/A| 0| 0| 0| 0|
| lk_250 | | | | | | | |
| TS_amb_gen_syn_pcie_core_ep_c| 16.000ns| 16.000ns| 4.000ns| 0| 0| 105858| 14|
| lk_62_5 | | | | | | | |
| TS_TO_maind_test0reg_1_LDC | 16.000ns| 4.000ns| N/A| 0| 0| 14| 0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
All constraints were met.
Generating Pad Report.
All signals are completely routed.
Par:283 - There are 41 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 57 secs
Total CPU time to PAR completion: 57 secs
Peak Memory Usage: 378 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 44
Number of info messages: 0
Writing design to file sp605_lx45t_core.ncd
PAR done!
Executing "C:\Xilinx\14.5\ISE_DS\ISE\bin\nt\trce.exe" -e 3 -s 3 -n 3 -fastpaths "sp605_lx45t_core.ncd" "sp605_lx45t_core.pcf" -o "sp605_lx45t_core_postpar.twr"
Release 14.5 - Trace (nt)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file '6slx45t.nph' in environment
C:\Xilinx\14.5\ISE_DS\ISE\.
"sp605_lx45t_core" is an NCD, version 3.2, device xc6slx45t, package fgg484,
speed -3
--------------------------------------------------------------------------------
Release 14.5 Trace (nt)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
C:\Xilinx\14.5\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -e 3 -s 3 -n 3 -fastpaths
sp605_lx45t_core.ncd sp605_lx45t_core.pcf -o sp605_lx45t_core_postpar.twr
Design file: sp605_lx45t_core.ncd
Physical constraint file: sp605_lx45t_core.pcf
Device,speed: xc6slx45t,-3 (PRODUCTION 1.23 2013-03-26)
Report level: error report
--------------------------------------------------------------------------------
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in
the unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of
this model, and for more information on accounting for different loading conditions, please see the device datasheet.
Timing summary:
---------------
Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)
Constraints cover 105917 paths, 0 nets, and 20077 connections
Design statistics:
Minimum period: 16.000ns (Maximum frequency: 62.500MHz)
Maximum path delay from/to any node: 4.000ns
Analysis completed Wed Jul 17 00:52:36 2013
--------------------------------------------------------------------------------
Generating Report ...
Number of warnings: 0
Number of info messages: 3
Total time: 12 secs
Executing "C:\Xilinx\14.5\ISE_DS\ISE\bin\nt\bitgen.exe" -intstyle ise -f "sp605_lx45t_core.ut" "sp605_lx45t_core.ncd" "sp605_lx45t_core" "sp605_lx45t_core.pcf"
PhysDesignRules:372 - Gated clock. Clock net
main/d_test0/reset_reg_test_mode_AND_577_o is sourced by a combinatorial pin.
This is not good design practice. Use the CE pin to control the loading of
data into the flip-flop.
PhysDesignRules:372 - Gated clock. Clock net amb/clk30k is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/rx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf
/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM9_RAMD_O> is incomplete. The signal
does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/rx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf
/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMD_O> is incomplete. The signal
does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/rx/fifo1_cmpl/U0/xst_fifo_generator/gconvfifo.rf/grf.r
f/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM9_RAMD_O> is incomplete. The signal
does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/rx/fifo1_cmpl/U0/xst_fifo_generator/gconvfifo.rf/grf.r
f/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMD_O> is incomplete. The signal
does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/rx/fifo1_cmpl/U0/xst_fifo_generator/gconvfifo.rf/grf.r
f/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMD_O> is incomplete. The signal
does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/rx/fifo1_cmpl/U0/xst_fifo_generator/gconvfifo.rf/grf.r
f/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM10_RAMD_O> is incomplete. The signal
does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/rx/fifo1_cmpl/U0/xst_fifo_generator/gconvfifo.rf/grf.r
f/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMD_O> is incomplete. The signal
does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/rx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf
/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM12_RAMA_DPO> is incomplete. The signal
does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/rx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf
/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM12_RAMB_DPO> is incomplete. The signal
does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/rx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf
/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM12_RAMD_O> is incomplete. The signal
does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/rx/fifo1_cmpl/U0/xst_fifo_generator/gconvfifo.rf/grf.r
f/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM12_RAMB_DPO> is incomplete. The signal
does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/rx/fifo1_cmpl/U0/xst_fifo_generator/gconvfifo.rf/grf.r
f/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM12_RAMC_DPO> is incomplete. The signal
does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/rx/fifo1_cmpl/U0/xst_fifo_generator/gconvfifo.rf/grf.r
f/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM12_RAMD_O> is incomplete. The signal
does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/rx/fifo1_cmpl/U0/xst_fifo_generator/gconvfifo.rf/grf.r
f/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM11_RAMC_DPO> is incomplete. The signal
does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/rx/fifo1_cmpl/U0/xst_fifo_generator/gconvfifo.rf/grf.r
f/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM11_RAMD_O> is incomplete. The signal
does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/rx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf
/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMD_O> is incomplete. The signal
does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/rx/fifo1_cmpl/U0/xst_fifo_generator/gconvfifo.rf/grf.r
f/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMD_O> is incomplete. The signal
does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/rx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf
/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMD_O> is incomplete. The signal
does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/rx/fifo1_cmpl/U0/xst_fifo_generator/gconvfifo.rf/grf.r
f/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMD_O> is incomplete. The signal
does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/rx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf
/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMD_O> is incomplete. The signal
does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/rx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf
/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMD_O> is incomplete. The signal
does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/rx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf
/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM10_RAMD_O> is incomplete. The signal
does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/rx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf
/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMD_O> is incomplete. The signal
does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/rx/fifo1_cmpl/U0/xst_fifo_generator/gconvfifo.rf/grf.r
f/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMD_O> is incomplete. The signal
does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/rx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf
/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM8_RAMD_O> is incomplete. The signal
does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/rx/fifo1_cmpl/U0/xst_fifo_generator/gconvfifo.rf/grf.r
f/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM8_RAMD_O> is incomplete. The signal
does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/rx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf
/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM11_RAMC_DPO> is incomplete. The signal
does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/rx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf
/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM11_RAMD_O> is incomplete. The signal
does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/rx/fifo1_cmpl/U0/xst_fifo_generator/gconvfifo.rf/grf.r
f/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMD_O> is incomplete. The signal
does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/rx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf
/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMD_O> is incomplete. The signal
does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/tx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf
/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMD_O> is incomplete. The signal
does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/tx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf
/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMD_O> is incomplete. The signal
does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/tx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf
/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM9_RAMD_O> is incomplete. The signal
does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/tx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf
/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM10_RAMD_O> is incomplete. The signal
does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/tx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf
/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMD_O> is incomplete. The signal
does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/tx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf
/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM11_RAMD_O> is incomplete. The signal
does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/tx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf
/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM8_RAMD_O> is incomplete. The signal
does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/tx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf
/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMD_O> is incomplete. The signal
does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/tx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf
/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMD_O> is incomplete. The signal
does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/tx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf
/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMD_O> is incomplete. The signal
does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/tx/fifo0_reg/U0/xst_fifo_generator/gconvfifo.rf/grf.rf
/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMD_O> is incomplete. The signal
does not drive any load pins in the design.
Implementation ver1->rev1: 0 error(s), 567 warning(s)
Implementation ended with warning(s).