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AMBPEX5_v20_SX50T_CORE
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00001 -------------------------------------------------------------------------------- 00002 -- This file is owned and controlled by Xilinx and must be used -- 00003 -- solely for design, simulation, implementation and creation of -- 00004 -- design files limited to Xilinx devices or technologies. Use -- 00005 -- with non-Xilinx devices or technologies is expressly prohibited -- 00006 -- and immediately terminates your license. -- 00007 -- -- 00008 -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- 00009 -- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- 00010 -- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- 00011 -- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- 00012 -- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- 00013 -- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- 00014 -- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- 00015 -- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- 00016 -- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- 00017 -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- 00018 -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- 00019 -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- 00020 -- FOR A PARTICULAR PURPOSE. -- 00021 -- -- 00022 -- Xilinx products are not intended for use in life support -- 00023 -- appliances, devices, or systems. Use in such applications are -- 00024 -- expressly prohibited. -- 00025 -- -- 00026 -- (c) Copyright 1995-2006 Xilinx, Inc. -- 00027 -- All rights reserved. -- 00028 -------------------------------------------------------------------------------- 00029 -- You must compile the wrapper file ctrl_multiplier_v1_0.vhd when simulating 00030 -- the core, ctrl_multiplier_v1_0. When compiling the wrapper file, be sure to 00031 -- reference the XilinxCoreLib VHDL simulation library. For detailed 00032 -- instructions, please refer to the "CORE Generator Help". 00033 00034 -- The synopsys directives "translate_off/translate_on" specified 00035 -- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity 00036 -- synthesis tools. Ensure they are correct for your synthesis tool(s). 00037 00038 LIBRARY ieee; 00039 USE ieee.std_logic_1164.ALL; 00040 -- synopsys translate_off 00041 Library XilinxCoreLib; 00042 -- synopsys translate_on 00043 ENTITY ctrl_multiplier_v1_0 IS 00044 port ( 00045 clk: IN std_logic; 00046 a: IN std_logic_VECTOR(15 downto 0); 00047 b: IN std_logic_VECTOR(10 downto 0); 00048 p: OUT std_logic_VECTOR(26 downto 0)); 00049 END ctrl_multiplier_v1_0; 00050 00051 ARCHITECTURE ctrl_multiplier_v1_0_a OF ctrl_multiplier_v1_0 IS 00052 -- synopsys translate_off 00053 component wrapped_ctrl_multiplier_v1_0 00054 port ( 00055 clk: IN std_logic; 00056 a: IN std_logic_VECTOR(15 downto 0); 00057 b: IN std_logic_VECTOR(10 downto 0); 00058 p: OUT std_logic_VECTOR(26 downto 0)); 00059 end component; 00060 00061 -- Configuration specification 00062 for all : wrapped_ctrl_multiplier_v1_0 use entity XilinxCoreLib.mult_gen_v9_0(behavioral) 00063 generic map( 00064 c_a_width => 16, 00065 c_b_type => 1, 00066 c_ce_overrides_sclr => 0, 00067 c_opt_goal => 1, 00068 c_has_sclr => 0, 00069 c_round_pt => 0, 00070 c_out_high => 26 , 00071 c_mult_type => 0, 00072 c_ccm_imp => 0, 00073 c_has_load_done => 0, 00074 c_pipe_stages => 1, 00075 c_has_ce => 0, 00076 c_has_zero_detect => 0, 00077 c_round_output => 0, 00078 c_mem_init_prefix => "mgv9", 00079 c_xdevicefamily => "virtex4", 00080 c_a_type => 1, 00081 c_out_low => 0, 00082 c_b_width => 11 , 00083 c_b_value => "10000001" ); 00084 -- synopsys translate_on 00085 BEGIN 00086 -- synopsys translate_off 00087 U0 : wrapped_ctrl_multiplier_v1_0 00088 port map ( 00089 clk => clk, 00090 a => a, 00091 b => b, 00092 p => p); 00093 -- synopsys translate_on 00094 00095 END ctrl_multiplier_v1_0_a; 00096
1.7.4