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AMBPEX5_v20_SX50T_CORE
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00001 -------------------------------------------------------------------------------- 00002 -- This file is owned and controlled by Xilinx and must be used -- 00003 -- solely for design, simulation, implementation and creation of -- 00004 -- design files limited to Xilinx devices or technologies. Use -- 00005 -- with non-Xilinx devices or technologies is expressly prohibited -- 00006 -- and immediately terminates your license. -- 00007 -- -- 00008 -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- 00009 -- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- 00010 -- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- 00011 -- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- 00012 -- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- 00013 -- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- 00014 -- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- 00015 -- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- 00016 -- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- 00017 -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- 00018 -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- 00019 -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- 00020 -- FOR A PARTICULAR PURPOSE. -- 00021 -- -- 00022 -- Xilinx products are not intended for use in life support -- 00023 -- appliances, devices, or systems. Use in such applications are -- 00024 -- expressly prohibited. -- 00025 -- -- 00026 -- (c) Copyright 1995-2003 Xilinx, Inc. -- 00027 -- All rights reserved. -- 00028 -------------------------------------------------------------------------------- 00029 -- You must compile the wrapper file ctrl_mux16x16.vhd when simulating 00030 -- the core, ctrl_mux16x16. When compiling the wrapper file, be sure to 00031 -- reference the XilinxCoreLib VHDL simulation library. For detailed 00032 -- instructions, please refer to the "CORE Generator Guide". 00033 00034 -- The synopsys directives "translate_off/translate_on" specified 00035 -- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity 00036 -- synthesis tools. Ensure they are correct for your synthesis tool(s). 00037 00038 -- synopsys translate_off 00039 LIBRARY ieee; 00040 USE ieee.std_logic_1164.ALL; 00041 00042 Library XilinxCoreLib; 00043 ENTITY ctrl_mux16x16 IS 00044 port ( 00045 MA: IN std_logic_VECTOR(15 downto 0); 00046 MB: IN std_logic_VECTOR(15 downto 0); 00047 MC: IN std_logic_VECTOR(15 downto 0); 00048 MD: IN std_logic_VECTOR(15 downto 0); 00049 ME: IN std_logic_VECTOR(15 downto 0); 00050 MF: IN std_logic_VECTOR(15 downto 0); 00051 MG: IN std_logic_VECTOR(15 downto 0); 00052 MH: IN std_logic_VECTOR(15 downto 0); 00053 MAA: IN std_logic_VECTOR(15 downto 0); 00054 MAB: IN std_logic_VECTOR(15 downto 0); 00055 MAC: IN std_logic_VECTOR(15 downto 0); 00056 MAD: IN std_logic_VECTOR(15 downto 0); 00057 MAE: IN std_logic_VECTOR(15 downto 0); 00058 MAF: IN std_logic_VECTOR(15 downto 0); 00059 MAG: IN std_logic_VECTOR(15 downto 0); 00060 MAH: IN std_logic_VECTOR(15 downto 0); 00061 S: IN std_logic_VECTOR(3 downto 0); 00062 O: OUT std_logic_VECTOR(15 downto 0)); 00063 END ctrl_mux16x16; 00064 00065 ARCHITECTURE ctrl_mux16x16_a OF ctrl_mux16x16 IS 00066 00067 component wrapped_ctrl_mux16x16 00068 port ( 00069 MA: IN std_logic_VECTOR(15 downto 0); 00070 MB: IN std_logic_VECTOR(15 downto 0); 00071 MC: IN std_logic_VECTOR(15 downto 0); 00072 MD: IN std_logic_VECTOR(15 downto 0); 00073 ME: IN std_logic_VECTOR(15 downto 0); 00074 MF: IN std_logic_VECTOR(15 downto 0); 00075 MG: IN std_logic_VECTOR(15 downto 0); 00076 MH: IN std_logic_VECTOR(15 downto 0); 00077 MAA: IN std_logic_VECTOR(15 downto 0); 00078 MAB: IN std_logic_VECTOR(15 downto 0); 00079 MAC: IN std_logic_VECTOR(15 downto 0); 00080 MAD: IN std_logic_VECTOR(15 downto 0); 00081 MAE: IN std_logic_VECTOR(15 downto 0); 00082 MAF: IN std_logic_VECTOR(15 downto 0); 00083 MAG: IN std_logic_VECTOR(15 downto 0); 00084 MAH: IN std_logic_VECTOR(15 downto 0); 00085 S: IN std_logic_VECTOR(3 downto 0); 00086 O: OUT std_logic_VECTOR(15 downto 0)); 00087 end component; 00088 00089 -- Configuration specification 00090 for all : wrapped_ctrl_mux16x16 use entity XilinxCoreLib.C_MUX_BUS_V6_0(behavioral) 00091 generic map( 00092 c_has_aset => 0, 00093 c_has_en => 0, 00094 c_sync_priority => 1, 00095 c_has_sclr => 0, 00096 c_width => 16, 00097 c_height => 0, 00098 c_enable_rlocs => 0, 00099 c_sel_width => 4, 00100 c_latency => 0, 00101 c_ainit_val => "0000000000000000" , 00102 c_has_ce => 0, 00103 c_mux_type => 0, 00104 c_has_aclr => 0, 00105 c_sync_enable => 0, 00106 c_has_ainit => 0, 00107 c_sinit_val => "0000000000000000", 00108 c_has_sset => 0, 00109 c_has_sinit => 0, 00110 c_has_q => 0, 00111 c_has_o => 1, 00112 c_inputs => 16); 00113 BEGIN 00114 00115 U0 : wrapped_ctrl_mux16x16 00116 port map ( 00117 MA => MA, 00118 MB => MB, 00119 MC => MC, 00120 MD => MD, 00121 ME => ME, 00122 MF => MF, 00123 MG => MG, 00124 MH => MH, 00125 MAA => MAA, 00126 MAB => MAB, 00127 MAC => MAC, 00128 MAD => MAD, 00129 MAE => MAE, 00130 MAF => MAF, 00131 MAG => MAG, 00132 MAH => MAH, 00133 S => S, 00134 O => O); 00135 END ctrl_mux16x16_a; 00136 00137 -- synopsys translate_on 00138
1.7.4