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AMBPEX5_v20_SX50T_CORE
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00001 -------------------------------------------------------------------------------- 00002 -- This file is owned and controlled by Xilinx and must be used -- 00003 -- solely for design, simulation, implementation and creation of -- 00004 -- design files limited to Xilinx devices or technologies. Use -- 00005 -- with non-Xilinx devices or technologies is expressly prohibited -- 00006 -- and immediately terminates your license. -- 00007 -- -- 00008 -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- 00009 -- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- 00010 -- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- 00011 -- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- 00012 -- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- 00013 -- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- 00014 -- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- 00015 -- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- 00016 -- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- 00017 -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- 00018 -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- 00019 -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- 00020 -- FOR A PARTICULAR PURPOSE. -- 00021 -- -- 00022 -- Xilinx products are not intended for use in life support -- 00023 -- appliances, devices, or systems. Use in such applications are -- 00024 -- expressly prohibited. -- 00025 -- -- 00026 -- (c) Copyright 1995-2003 Xilinx, Inc. -- 00027 -- All rights reserved. -- 00028 -------------------------------------------------------------------------------- 00029 -- You must compile the wrapper file ctrl_mux8x48.vhd when simulating 00030 -- the core, ctrl_mux8x48. When compiling the wrapper file, be sure to 00031 -- reference the XilinxCoreLib VHDL simulation library. For detailed 00032 -- instructions, please refer to the "CORE Generator Guide". 00033 00034 -- The synopsys directives "translate_off/translate_on" specified 00035 -- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity 00036 -- synthesis tools. Ensure they are correct for your synthesis tool(s). 00037 00038 -- synopsys translate_off 00039 LIBRARY ieee; 00040 USE ieee.std_logic_1164.ALL; 00041 00042 Library XilinxCoreLib; 00043 ENTITY ctrl_mux8x48 IS 00044 port ( 00045 MA: IN std_logic_VECTOR(47 downto 0); 00046 MB: IN std_logic_VECTOR(47 downto 0); 00047 MC: IN std_logic_VECTOR(47 downto 0); 00048 MD: IN std_logic_VECTOR(47 downto 0); 00049 ME: IN std_logic_VECTOR(47 downto 0); 00050 MF: IN std_logic_VECTOR(47 downto 0); 00051 MG: IN std_logic_VECTOR(47 downto 0); 00052 MH: IN std_logic_VECTOR(47 downto 0); 00053 S: IN std_logic_VECTOR(2 downto 0); 00054 O: OUT std_logic_VECTOR(47 downto 0)); 00055 END ctrl_mux8x48; 00056 00057 ARCHITECTURE ctrl_mux8x48_a OF ctrl_mux8x48 IS 00058 00059 component wrapped_ctrl_mux8x48 00060 port ( 00061 MA: IN std_logic_VECTOR(47 downto 0); 00062 MB: IN std_logic_VECTOR(47 downto 0); 00063 MC: IN std_logic_VECTOR(47 downto 0); 00064 MD: IN std_logic_VECTOR(47 downto 0); 00065 ME: IN std_logic_VECTOR(47 downto 0); 00066 MF: IN std_logic_VECTOR(47 downto 0); 00067 MG: IN std_logic_VECTOR(47 downto 0); 00068 MH: IN std_logic_VECTOR(47 downto 0); 00069 S: IN std_logic_VECTOR(2 downto 0); 00070 O: OUT std_logic_VECTOR(47 downto 0)); 00071 end component; 00072 00073 -- Configuration specification 00074 for all : wrapped_ctrl_mux8x48 use entity XilinxCoreLib.C_MUX_BUS_V6_0(behavioral) 00075 generic map( 00076 c_has_aset => 0, 00077 c_has_en => 0, 00078 c_sync_priority => 1, 00079 c_has_sclr => 0, 00080 c_width => 48, 00081 c_height => 0, 00082 c_enable_rlocs => 0, 00083 c_sel_width => 3, 00084 c_latency => 0, 00085 c_ainit_val => "000000000000000000000000000000000000000000000000" , 00086 c_has_ce => 0, 00087 c_mux_type => 0, 00088 c_has_aclr => 0, 00089 c_sync_enable => 0, 00090 c_has_ainit => 0, 00091 c_sinit_val => "000000000000000000000000000000000000000000000000" , 00092 c_has_sset => 0, 00093 c_has_sinit => 0, 00094 c_has_q => 0, 00095 c_has_o => 1, 00096 c_inputs => 8); 00097 BEGIN 00098 00099 U0 : wrapped_ctrl_mux8x48 00100 port map ( 00101 MA => MA, 00102 MB => MB, 00103 MC => MC, 00104 MD => MD, 00105 ME => ME, 00106 MF => MF, 00107 MG => MG, 00108 MH => MH, 00109 S => S, 00110 O => O); 00111 END ctrl_mux8x48_a; 00112 00113 -- synopsys translate_on 00114
1.7.4