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AMBPEX5_v20_SX50T_CORE
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00001 --------------------------------------------------------------------------------------------------- 00002 -- 00003 -- Title : ctrl_thdac 00004 -- Design : ADM2 00005 -- Author : Ilya Ivanov 00006 -- Company : Instrumental System 00007 -- 00008 -- Version : 1.0 00009 --------------------------------------------------------------------------------------------------- 00010 -- 00011 -- Description : Управление ИПН 00012 -- 00013 --------------------------------------------------------------------------------------------------- 00014 00015 00016 library IEEE; 00017 use IEEE.STD_LOGIC_1164.all; 00018 use IEEE.std_logic_unsigned.all ; 00019 00020 00021 entity ctrl_thdac is 00022 port( 00023 reset : in STD_LOGIC; 00024 clk : in STD_LOGIC; 00025 start : in STD_LOGIC; 00026 data_dac : in STD_LOGIC_VECTOR(11 downto 0); 00027 clkDAC_out : out STD_LOGIC; 00028 ld : out STD_LOGIC; 00029 ready : out STD_LOGIC; 00030 thrs : out STD_LOGIC; 00031 sdo_dac : out STD_LOGIC 00032 ); 00033 end ctrl_thdac; 00034 00035 00036 00037 architecture ctrl_thdac of ctrl_thdac is 00038 00039 signal counter : std_logic_vector(5 downto 0) ; -- counter for reset 00040 signal counter2 : std_logic_vector(7 downto 0) ; -- counter for reset 00041 signal counter_data : std_logic_vector(5 downto 0) ; -- counter for reset 00042 signal l_ready,l_ready2,l_clk:std_logic; 00043 signal l_data_dac : STD_LOGIC_VECTOR(11 downto 0); 00044 00045 begin 00046 thrs<=reset; 00047 pr_start: process( clk,reset ) 00048 begin 00049 if(reset='0') then 00050 l_ready<='0'; 00051 elsif( rising_edge( clk ) ) then 00052 if(start='1')then 00053 l_ready<='1'; 00054 l_data_dac<=data_dac; 00055 elsif(counter_data = "11000")then 00056 l_ready<='0'; 00057 end if; 00058 00059 end if; 00060 end process; 00061 00062 pr_count: process( clk,reset ) 00063 begin 00064 if(reset='0') then 00065 counter <= (others => '0') ; 00066 counter_data <= (others => '0') ; 00067 elsif( rising_edge( clk ) ) then 00068 if(l_ready='1')then 00069 counter <= counter + 1 ; 00070 if (counter = "01010") then 00071 counter <= (others => '0') ; 00072 counter_data <= counter_data + 1 ; 00073 end if; 00074 else 00075 counter <= (others => '0') ; 00076 counter_data <= (others => '0') ; 00077 end if; 00078 end if; 00079 end process; 00080 00081 00082 pr_clk_out: process( clk,reset ) 00083 begin 00084 if(reset='0') then 00085 l_clk<='0'; 00086 clkDAC_out<='0'; 00087 elsif( rising_edge( clk ) ) then 00088 if(counter = "101")then 00089 l_clk<=not l_clk; 00090 end if; 00091 clkDAC_out<=l_clk; 00092 end if; 00093 end process; 00094 --clkDAC_out<=clk; 00095 pr_data_out: process( clk,reset ) 00096 begin 00097 if(reset='0') then 00098 sdo_dac<='0'; 00099 elsif( rising_edge( clk ) ) then 00100 if(counter = "00010" )then 00101 if( counter_data="00000")then 00102 sdo_dac<=l_data_dac(11); 00103 elsif( counter_data="00010")then 00104 sdo_dac<=l_data_dac(10); 00105 elsif( counter_data="00100")then 00106 sdo_dac<=l_data_dac(9); 00107 elsif( counter_data="00110")then 00108 sdo_dac<=l_data_dac(8); 00109 elsif( counter_data="01000")then 00110 sdo_dac<=l_data_dac(7); 00111 elsif( counter_data="01010")then 00112 sdo_dac<=l_data_dac(6); 00113 elsif( counter_data="01100")then 00114 sdo_dac<=l_data_dac(5); 00115 elsif( counter_data="01110")then 00116 sdo_dac<=l_data_dac(4); 00117 elsif( counter_data="10000")then 00118 sdo_dac<=l_data_dac(3); 00119 elsif( counter_data="10010")then 00120 sdo_dac<=l_data_dac(2); 00121 elsif( counter_data="10100")then 00122 sdo_dac<=l_data_dac(1); 00123 elsif( counter_data="10110")then 00124 sdo_dac<=l_data_dac(0); 00125 end if; 00126 end if; 00127 00128 00129 end if; 00130 end process; 00131 00132 00133 pr_count2: process( clk,reset ) 00134 begin 00135 if(reset='0') then 00136 counter2 <= (others => '0') ; 00137 elsif( rising_edge( clk ) ) then 00138 if(l_ready2='1')then 00139 counter2 <= counter2 + 1 ; 00140 else 00141 counter2 <= (others => '0') ; 00142 end if; 00143 end if; 00144 end process; 00145 00146 pr_ready2: process( clk,reset ) 00147 begin 00148 if(reset='0') then 00149 l_ready2<='0'; 00150 ld<='0'; 00151 elsif( rising_edge( clk ) ) then 00152 if(counter_data = "10111")then 00153 l_ready2<='1'; 00154 elsif(counter2 = "1010")then 00155 ld<='1'; 00156 elsif(counter2 = "11111")then 00157 ld<='0'; 00158 elsif(counter2 = "110110")then 00159 l_ready2<='0'; 00160 00161 end if; 00162 end if; 00163 end process; 00164 00165 pr_redy: process( clk,reset ) 00166 begin 00167 if(reset='0') then 00168 ready<='1'; 00169 elsif( rising_edge( clk ) ) then 00170 ready<=not (l_ready or l_ready2); 00171 end if; 00172 end process; 00173 00174 00175 end ctrl_thdac;
1.7.4