Граф наследования:axi_basic_rx_null_gen:
Architectures | |
| TRANS | Architecture |
Libraries | |
| ieee | |
Packages | |
| std_logic_1164 | |
| std_logic_unsigned | |
Generics | |
| C_DATA_WIDTH | integer := 128 |
| TCQ | integer := 1 |
| C_STRB_WIDTH | integer := 4 |
Ports | |
| M_AXIS_RX_TDATA | in std_logic_vector ( c_data_width- 1 downto 0 ) := ( others = > ' 0 ' ) |
| M_AXIS_RX_TVALID | in std_logic := ' 0 ' |
| M_AXIS_RX_TREADY | in std_logic := ' 0 ' |
| M_AXIS_RX_TLAST | in std_logic := ' 0 ' |
| M_AXIS_RX_TUSER | in std_logic_vector ( 21 downto 0 ) := ( others = > ' 0 ' ) |
| NULL_RX_TVALID | out std_logic |
| NULL_RX_TLAST | out std_logic |
| NULL_RX_TSTRB | out std_logic_vector ( c_strb_width- 1 downto 0 ) |
| NULL_RDST_RDY | out std_logic |
| NULL_IS_EOF | out std_logic_vector ( 4 downto 0 ) |
| USER_CLK | in std_logic := ' 0 ' |
| USER_RST | in std_logic := ' 0 ' |
Подробное описание
См. определение в файле axi_basic_rx_null_gen.vhd строка 71
Объявления и описания членов класса находятся в файле:
- pcie_src/pcie_core64_m1/source_virtex6/axi_basic_rx_null_gen.vhd
