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AMBPEX5_v20_SX50T_CORE
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00001 -------------------------------------------------------------------------------- 00002 -- This file is owned and controlled by Xilinx and must be used -- 00003 -- solely for design, simulation, implementation and creation of -- 00004 -- design files limited to Xilinx devices or technologies. Use -- 00005 -- with non-Xilinx devices or technologies is expressly prohibited -- 00006 -- and immediately terminates your license. -- 00007 -- -- 00008 -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- 00009 -- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- 00010 -- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- 00011 -- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- 00012 -- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- 00013 -- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- 00014 -- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- 00015 -- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- 00016 -- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- 00017 -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- 00018 -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- 00019 -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- 00020 -- FOR A PARTICULAR PURPOSE. -- 00021 -- -- 00022 -- Xilinx products are not intended for use in life support -- 00023 -- appliances, devices, or systems. Use in such applications are -- 00024 -- expressly prohibited. -- 00025 -- -- 00026 -- (c) Copyright 1995-2006 Xilinx, Inc. -- 00027 -- All rights reserved. -- 00028 -------------------------------------------------------------------------------- 00029 -- You must compile the wrapper file ctrl_fifo1024x65_v5.vhd when simulating 00030 -- the core, ctrl_fifo1024x65_v5. When compiling the wrapper file, be sure to 00031 -- reference the XilinxCoreLib VHDL simulation library. For detailed 00032 -- instructions, please refer to the "CORE Generator Help". 00033 00034 -- The synopsys directives "translate_off/translate_on" specified 00035 -- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity 00036 -- synthesis tools. Ensure they are correct for your synthesis tool(s). 00037 00038 LIBRARY ieee; 00039 USE ieee.std_logic_1164.ALL; 00040 -- synopsys translate_off 00041 Library XilinxCoreLib; 00042 -- synopsys translate_on 00043 ENTITY ctrl_fifo1024x65_v5 IS 00044 port ( 00045 din: IN std_logic_VECTOR(64 downto 0); 00046 rd_clk: IN std_logic; 00047 rd_en: IN std_logic; 00048 rst: IN std_logic; 00049 wr_clk: IN std_logic; 00050 wr_en: IN std_logic; 00051 dout: OUT std_logic_VECTOR(64 downto 0); 00052 empty: OUT std_logic; 00053 full: OUT std_logic; 00054 prog_empty: OUT std_logic; 00055 prog_full: OUT std_logic; 00056 rd_data_count: OUT std_logic_VECTOR(0 downto 0); 00057 wr_data_count: OUT std_logic_VECTOR(0 downto 0)); 00058 END ctrl_fifo1024x65_v5; 00059 00060 ARCHITECTURE ctrl_fifo1024x65_v5_a OF ctrl_fifo1024x65_v5 IS 00061 -- synopsys translate_off 00062 component wrapped_ctrl_fifo1024x65_v5 00063 port ( 00064 din: IN std_logic_VECTOR(64 downto 0); 00065 rd_clk: IN std_logic; 00066 rd_en: IN std_logic; 00067 rst: IN std_logic; 00068 wr_clk: IN std_logic; 00069 wr_en: IN std_logic; 00070 dout: OUT std_logic_VECTOR(64 downto 0); 00071 empty: OUT std_logic; 00072 full: OUT std_logic; 00073 prog_empty: OUT std_logic; 00074 prog_full: OUT std_logic; 00075 rd_data_count: OUT std_logic_VECTOR(0 downto 0); 00076 wr_data_count: OUT std_logic_VECTOR(0 downto 0)); 00077 end component; 00078 00079 -- Configuration specification 00080 for all : wrapped_ctrl_fifo1024x65_v5 use entity XilinxCoreLib.fifo_generator_v3_3(behavioral) 00081 generic map( 00082 c_rd_freq => 100, 00083 c_wr_response_latency => 1, 00084 c_has_srst => 0, 00085 c_has_rd_data_count => 1, 00086 c_din_width => 65 , 00087 c_has_wr_data_count => 1, 00088 c_implementation_type => 2, 00089 c_family => "spartan3", 00090 c_has_wr_rst => 0, 00091 c_wr_freq => 100 , 00092 c_underflow_low => 0, 00093 c_has_meminit_file => 0, 00094 c_has_overflow => 0, 00095 c_preload_latency => 1, 00096 c_dout_width => 65 , 00097 c_rd_depth => 1024, 00098 c_default_value => "BlankString", 00099 c_mif_file_name => "BlankString", 00100 c_has_underflow => 0, 00101 c_has_rd_rst => 0, 00102 c_has_almost_full => 0, 00103 c_has_rst => 1, 00104 c_data_count_width => 10 , 00105 c_has_wr_ack => 0, 00106 c_wr_ack_low => 0, 00107 c_common_clock => 0, 00108 c_rd_pntr_width => 10 , 00109 c_has_almost_empty => 0, 00110 c_rd_data_count_width => 1, 00111 c_enable_rlocs => 0, 00112 c_wr_pntr_width => 10 , 00113 c_overflow_low => 0, 00114 c_prog_empty_type => 1, 00115 c_optimization_mode => 0, 00116 c_wr_data_count_width => 1, 00117 c_preload_regs => 0, 00118 c_dout_rst_val => "0" , 00119 c_has_data_count => 0, 00120 c_prog_full_thresh_negate_val => 991 , 00121 c_wr_depth => 1024, 00122 c_prog_empty_thresh_negate_val => 33, 00123 c_prog_empty_thresh_assert_val => 32, 00124 c_has_valid => 0, 00125 c_init_wr_pntr_val => 0, 00126 c_prog_full_thresh_assert_val => 992 , 00127 c_use_fifo16_flags => 0, 00128 c_has_backup => 0, 00129 c_valid_low => 0, 00130 c_prim_fifo_type => "1kx36", 00131 c_count_type => 0, 00132 c_prog_full_type => 1, 00133 c_memory_type => 1); 00134 -- synopsys translate_on 00135 BEGIN 00136 -- synopsys translate_off 00137 U0 : wrapped_ctrl_fifo1024x65_v5 00138 port map ( 00139 din => din, 00140 rd_clk => rd_clk, 00141 rd_en => rd_en, 00142 rst => rst, 00143 wr_clk => wr_clk, 00144 wr_en => wr_en, 00145 dout => dout, 00146 empty => empty, 00147 full => full, 00148 prog_empty => prog_empty, 00149 prog_full => prog_full, 00150 rd_data_count => rd_data_count, 00151 wr_data_count => wr_data_count); 00152 -- synopsys translate_on 00153 00154 END ctrl_fifo1024x65_v5_a; 00155
1.7.4