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DS_DMA
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00001 ------------------------------------------------------------------------------- 00002 -- 00003 -- Title : core64_tx_engine 00004 -- Author : Dmitry Smekhov 00005 -- Company : Instrumental Systems 00006 -- E-mail : dsmv@insys.ru 00007 -- 00008 -- Version : 1.0 00009 -- 00010 ------------------------------------------------------------------------------- 00011 -- 00012 -- Description : Формирователь пакетов 00013 -- 00014 ------------------------------------------------------------------------------- 00015 00016 library ieee; 00017 use ieee.std_logic_1164.all; 00018 00019 use work.core64_type_pkg.all; 00020 00021 package core64_tx_engine_pkg is 00022 00023 component core64_tx_engine is 00024 port( 00025 00026 --- General --- 00027 rstp : in std_logic; --! 1 - сброс 00028 clk : in std_logic; --! тактовая частота ядра - 250 MHz 00029 00030 trn_tx : out type_trn_tx; --! передача пакета 00031 trn_tx_back : in type_trn_tx_back; --! готовность к передаче пакета 00032 00033 completer_id : in std_logic_vector( 15 downto 0 ); --! идентификатор устройства 00034 00035 reg_access_back : in type_reg_access_back; --! запрос на доступ к регистрам 00036 00037 rx_tx_engine : in type_rx_tx_engine; --! обмен RX->TX 00038 tx_rx_engine : out type_tx_rx_engine; --! обмен TX->RX 00039 00040 tx_ext_fifo : out type_tx_ext_fifo; --! обмен TX->EXT_FIFO 00041 tx_ext_fifo_back: in type_tx_ext_fifo_back --! обмен TX->EXT_FIFO 00042 00043 ); 00044 end component; 00045 00046 end package; 00047 00048 library ieee; 00049 use ieee.std_logic_1164.all; 00050 use ieee.std_logic_arith.all; 00051 use ieee.std_logic_unsigned.all; 00052 00053 use work.core64_type_pkg.all; 00054 00055 library unisim; 00056 use unisim.vcomponents.all; 00057 00058 entity core64_tx_engine is 00059 port( 00060 00061 --- General --- 00062 rstp : in std_logic; --! 1 - сброс 00063 clk : in std_logic; --! тактовая частота ядра - 250 MHz 00064 00065 trn_tx : out type_trn_tx; --! передача пакета 00066 trn_tx_back : in type_trn_tx_back; --! готовность к передаче пакета 00067 00068 completer_id : in std_logic_vector( 15 downto 0 ); --! идентификатор устройства 00069 00070 reg_access_back : in type_reg_access_back; --! запрос на доступ к регистрам 00071 00072 rx_tx_engine : in type_rx_tx_engine; --! обмен RX->TX 00073 tx_rx_engine : out type_tx_rx_engine; --! обмен TX->RX 00074 00075 tx_ext_fifo : out type_tx_ext_fifo; --! обмен TX->EXT_FIFO 00076 tx_ext_fifo_back: in type_tx_ext_fifo_back --! обмен TX->EXT_FIFO 00077 00078 ); 00079 end core64_tx_engine; 00080 00081 00082 architecture core64_tx_engine of core64_tx_engine is 00083 00084 component ctrl_fifo64x67fw is 00085 port ( 00086 clk : in std_logic; 00087 rst : in std_logic; 00088 din : in std_logic_vector(66 downto 0); 00089 wr_en : in std_logic; 00090 rd_en : in std_logic; 00091 dout : out std_logic_vector(66 downto 0); 00092 full : out std_logic; 00093 empty : out std_logic; 00094 valid : out std_logic; 00095 prog_full : out std_logic; 00096 prog_empty : out std_logic 00097 ); 00098 end component; 00099 00100 function set_data( data_in : in std_logic_vector( 63 downto 0 ) ) return std_logic_vector is 00101 00102 variable ret : std_logic_vector( 63 downto 0 ); 00103 00104 begin 00105 00106 for ii in 0 to 63 loop 00107 if( data_in(ii)='1' ) then 00108 ret(ii):='1'; 00109 else 00110 ret(ii):='0'; 00111 end if; 00112 end loop; 00113 00114 return ret; 00115 00116 end set_data; 00117 00118 signal rstpz : std_logic; 00119 00120 type stp_type is ( s0, s1, s2, s3, s4, sr1, sr2, sr3, sr4, sr5, 00121 sw1, sw01, sw2, sw3, sw5, sw6 ); 00122 signal stp : stp_type; 00123 00124 signal fifo_din : std_logic_vector( 66 downto 0 ); 00125 signal fifo_wr : std_logic; 00126 signal fifo_rd : std_logic; 00127 signal fifo_dout : std_logic_vector( 66 downto 0 ); 00128 signal fifo_full : std_logic; 00129 signal fifo_empty : std_logic; 00130 signal fifo_valid : std_logic; 00131 signal fifo_paf : std_logic; 00132 signal fifo_pae : std_logic; 00133 00134 signal fifo_sof : std_logic; 00135 signal fifo_eof : std_logic; 00136 signal fifo_rrem : std_logic; 00137 signal fifo_data : std_logic_vector( 63 downto 0 ); 00138 signal reg_data : std_logic_vector( 31 downto 0 ); 00139 signal tlp_dw0 : std_logic_vector( 31 downto 0 ); 00140 signal tlp_dw1 : std_logic_vector( 31 downto 0 ); 00141 signal tlp_dw2 : std_logic_vector( 31 downto 0 ); 00142 signal tlp_dw3 : std_logic_vector( 31 downto 0 ); 00143 00144 signal cpl_status : std_logic_vector( 2 downto 0 ):="000"; 00145 signal cpl_byte_count : std_logic_vector( 11 downto 0 ) :=x"000"; 00146 00147 signal tlp_read_dw0 : std_logic_vector( 31 downto 0 ); 00148 signal tlp_read_dw1 : std_logic_vector( 31 downto 0 ); 00149 signal tlp_read_dw2 : std_logic_vector( 31 downto 0 ); 00150 signal tlp_read_dw3 : std_logic_vector( 31 downto 0 ); 00151 00152 signal max_read_size : std_logic_vector( 7 downto 0 ); 00153 signal read_tag : std_logic_vector( 7 downto 0 ); 00154 00155 signal req_cnt : std_logic_vector( 5 downto 0 ); --! счётчик запросов 00156 signal req_complete : std_logic; --! 1 - получены все ответы 00157 00158 signal wait_complete : std_logic; 00159 00160 signal complete_cnt : std_logic_vector( 9 downto 0 ); --! счётчик принятых слов 00161 signal timeout_cnt : std_logic_vector( 10 downto 0 ); --! ожидание ответа 00162 signal timeout_cnt_en : std_logic; 00163 signal timeout_error : std_logic; 00164 signal timeout_st0 : std_logic; 00165 signal rstpz1 : std_logic; 00166 00167 signal write_cnt_en : std_logic; 00168 signal write_cnt : std_logic_vector( 5 downto 0 ); --! счётчик слов в пакете 00169 signal write_cnt_pkg : std_logic_vector( 4 downto 0 ); --! счётчик пакетов 00170 signal write_cnt_eq : std_logic; 00171 signal write_cnt_pkg_eq: std_logic; 00172 signal write_state : std_logic; 00173 signal write_size : std_logic; --! 1 - пакет 256 байт, 0 - пакет 128 байт 00174 signal write_cnt_pkg_add : std_logic_vector( 1 downto 0 ); 00175 00176 signal tlp_write_dw0 : std_logic_vector( 31 downto 0 ); 00177 signal tlp_write_dw1 : std_logic_vector( 31 downto 0 ); 00178 signal tlp_write_dw2 : std_logic_vector( 31 downto 0 ); 00179 signal tlp_write_dw3 : std_logic_vector( 31 downto 0 ); 00180 00181 signal tlp_write_data : std_logic_vector( 63 downto 0 ); 00182 signal tlp_write_data_z: std_logic_vector( 31 downto 0 ); 00183 signal adr_cnt : std_logic_vector( 5 downto 0 ); 00184 00185 signal adr64 : std_logic; 00186 00187 begin 00188 00189 trn_tx.trn_td <= fifo_dout( 63 downto 0 ); 00190 trn_tx.trn_tsof_n <= fifo_dout( 64 ); 00191 trn_tx.trn_teof_n <= fifo_dout( 65 ); 00192 trn_tx.trn_trem_n( 7 downto 4 ) <= "0000"; 00193 trn_tx.trn_trem_n( 3 downto 0 ) <= (others=>fifo_dout( 66 ) ); 00194 00195 trn_tx.trn_tsrc_dsc_n <= '1'; 00196 trn_tx.trn_terrfwd_n <= '1'; 00197 00198 trn_tx.trn_tsrc_rdy_n <= fifo_empty or trn_tx_back.trn_tdst_rdy_n; 00199 fifo_rd <= not ( fifo_empty or trn_tx_back.trn_tdst_rdy_n ); 00200 00201 fifo0_reg: ctrl_fifo64x67fw 00202 port map( 00203 clk => clk, 00204 rst => rstpz, 00205 din => fifo_din, 00206 wr_en => fifo_wr , 00207 rd_en => fifo_rd , 00208 dout => fifo_dout, 00209 full => fifo_full, 00210 empty => fifo_empty, 00211 valid => fifo_valid, 00212 prog_full => fifo_paf, 00213 prog_empty => fifo_pae 00214 ); 00215 00216 rstpz <= rstp after 1 ns when rising_edge( clk ); 00217 00218 fifo_din <= fifo_rrem & fifo_eof & fifo_sof & set_data( fifo_data ); 00219 00220 pr_state: process( clk ) begin 00221 if( rising_edge( clk ) ) then 00222 00223 case( stp ) is 00224 when s0 => 00225 00226 if( fifo_paf='0' ) then 00227 00228 if( (rx_tx_engine.request_reg_wr='1' or rx_tx_engine.request_reg_rd='1') and trn_tx_back.trn_tbuf_av(2)='1' ) then 00229 stp <= s1 after 1 ns; 00230 elsif( tx_ext_fifo_back.req_rd='1' and trn_tx_back.trn_tbuf_av(0)='1' ) then 00231 stp <= sr1 after 1 ns; 00232 elsif( tx_ext_fifo_back.req_wr='1' and trn_tx_back.trn_tbuf_av(1)='1' ) then 00233 stp <= sw1 after 1 ns; 00234 end if; 00235 00236 end if; 00237 fifo_wr <= '0'; 00238 tx_rx_engine.complete_reg <= '0' after 1 ns; 00239 tx_ext_fifo.complete_ok <= '0' after 1 ns; 00240 tx_ext_fifo.complete_error <= '0' after 1 ns; 00241 write_cnt_en <= '0' after 1 ns; 00242 00243 00244 when s1 => 00245 if( reg_access_back.complete='1' ) then 00246 if( rx_tx_engine.request_reg_wr='1' ) then 00247 stp <= s4 after 1 ns; -- не отправляется при операции записи 00248 else 00249 stp <= s2 after 1 ns; 00250 end if; 00251 end if; 00252 00253 when s2 => 00254 fifo_sof <= '0' after 1 ns; 00255 fifo_eof <= '1' after 1 ns; 00256 fifo_rrem <= rx_tx_engine.request_reg_wr after 1 ns; 00257 fifo_data <= tlp_dw0 & tlp_dw1 after 1 ns; 00258 fifo_wr <= '1' after 1 ns; 00259 stp <= s3 after 1 ns; 00260 00261 when s3 => 00262 00263 fifo_sof <= '1' after 1 ns; 00264 fifo_eof <= '0' after 1 ns; 00265 fifo_rrem <= rx_tx_engine.request_reg_wr after 1 ns; 00266 fifo_data <= tlp_dw2 & tlp_dw3 after 1 ns; 00267 fifo_wr <= '1' after 1 ns; 00268 stp <= s4 after 1 ns; 00269 00270 when s4 => 00271 fifo_wr <= '0' after 1 ns; 00272 tx_rx_engine.complete_reg <= '1' after 1 ns; 00273 if( rx_tx_engine.request_reg_wr='0' and rx_tx_engine.request_reg_rd='0' ) then 00274 stp <= s0 after 1 ns; 00275 end if; 00276 00277 when sr1 => ---- Запрос на чтение данных из памяти ---- 00278 00279 if( req_cnt(5)='1' or (req_cnt(2)='1' and tx_ext_fifo_back.rd_size='0' ) ) then 00280 stp <= sr4 after 1 ns; 00281 else 00282 stp <= sr2 after 1 ns; 00283 end if; 00284 00285 when sr2 => 00286 wait_complete <= '1' after 1 ns; 00287 fifo_sof <= '0' after 1 ns; 00288 fifo_eof <= '1' after 1 ns; 00289 fifo_rrem <= '0' after 1 ns; 00290 fifo_data <= tlp_read_dw0 & tlp_read_dw1 after 1 ns; 00291 fifo_wr <= '1' after 1 ns; 00292 stp <= sr3 after 1 ns; 00293 00294 when sr3 => 00295 fifo_sof <= '1' after 1 ns; 00296 fifo_eof <= '0' after 1 ns; 00297 if( adr64='1' ) then 00298 fifo_data <= tlp_read_dw2 & tlp_read_dw3 after 1 ns; 00299 else 00300 fifo_data <= tlp_read_dw3 & tlp_read_dw3 after 1 ns; 00301 end if; 00302 00303 fifo_wr <= '1' after 1 ns; 00304 stp <= s0 after 1 ns; 00305 00306 -- when sr3 => ---- Ожидание завершения запроса ---- 00307 -- fifo_wr <= '0' after 1 ns; 00308 -- stp <= sr0 after 1 ns; 00309 00310 when sr4 => --- Проверка завершения запроса ---- 00311 if( req_complete='1' or timeout_error='1' ) then 00312 stp <= sr5 after 1 ns; 00313 else 00314 stp <= s0 after 1 ns; 00315 end if; 00316 00317 when sr5 => 00318 wait_complete <= '0' after 1 ns; 00319 tx_ext_fifo.complete_ok <= req_complete after 1 ns; 00320 tx_ext_fifo.complete_error <= timeout_error after 1 ns; 00321 if( tx_ext_fifo_back.req_rd='0' ) then 00322 stp <= s0 after 1 ns; 00323 end if; 00324 00325 00326 when sw1 => --- Запись 4 кБ --- 00327 00328 write_cnt_en <= not adr64 after 1 ns; 00329 stp <= sw01 after 1 ns; 00330 00331 when sw01 => --- Запись 4 кБ --- 00332 00333 00334 write_state <= '1' after 1 ns; 00335 00336 00337 fifo_sof <= '0' after 1 ns; 00338 fifo_eof <= '1' after 1 ns; 00339 fifo_rrem <= not adr64 after 1 ns; 00340 fifo_data <= tlp_write_dw0 & tlp_write_dw1 after 1 ns; 00341 fifo_wr <= '1' after 1 ns; 00342 00343 write_cnt_en <= '1' after 1 ns; 00344 stp <= sw2 after 1 ns; 00345 00346 00347 when sw2 => 00348 fifo_sof <= '1' after 1 ns; 00349 if( adr64='1' ) then 00350 fifo_data <= tlp_write_dw2 & tlp_write_dw3 after 1 ns; 00351 else 00352 fifo_data <= tlp_write_dw3 & tlp_write_data( 63 downto 32 ) after 1 ns; 00353 end if; 00354 00355 stp <= sw3 after 1 ns; 00356 00357 when sw3 => 00358 if( adr64='1' ) then 00359 fifo_data <= tlp_write_data after 1 ns; 00360 else 00361 fifo_data( 31 downto 0 ) <= tlp_write_data( 63 downto 32 ) after 1 ns; 00362 fifo_data( 63 downto 32 ) <= tlp_write_data_z( 31 downto 0 ) after 1 ns; 00363 end if; 00364 00365 00366 fifo_wr <= '1' after 1 ns; 00367 if( write_cnt_eq='1' ) then 00368 stp <= sw5 after 1 ns; 00369 -- elsif( fifo_paf='1' ) then 00370 -- stp <= sw4 after 1 ns; 00371 end if; 00372 00373 -- when sw4 => 00374 -- write_cnt_en <= '0' after 1 ns; 00375 -- fifo_wr <= '0' after 1 ns; 00376 -- if( fifo_paf='0' ) then 00377 -- stp <= sw3 after 1 ns; 00378 -- end if; 00379 00380 when sw5 => 00381 if( adr64='1' ) then 00382 fifo_data <= tlp_write_data after 1 ns; 00383 else 00384 fifo_data( 31 downto 0 ) <= tlp_write_data( 63 downto 32 ) after 1 ns; 00385 fifo_data( 63 downto 32 ) <= tlp_write_data_z( 31 downto 0 ) after 1 ns; 00386 end if; 00387 00388 fifo_eof <= '0' after 1 ns; 00389 write_cnt_en <= '0' after 1 ns; 00390 if( write_cnt_pkg_eq='1' ) then 00391 stp <= sw6 after 1 ns; 00392 else 00393 stp <= s0 after 1 ns; 00394 end if; 00395 00396 when sw6 => 00397 fifo_wr <= '0' after 1 ns; 00398 tx_ext_fifo.complete_ok <= '1' after 1 ns; 00399 tx_ext_fifo.complete_error <= '0' after 1 ns; 00400 write_state <= '0' after 1 ns; 00401 if( tx_ext_fifo_back.req_wr='0' ) then 00402 stp <= s0 after 1 ns; 00403 end if; 00404 00405 00406 00407 00408 00409 end case; 00410 00411 00412 00413 00414 00415 if( rstpz='1' ) then 00416 stp <= s0 after 1 ns; 00417 wait_complete <= '0' after 1 ns; 00418 write_state <= '0' after 1 ns; 00419 end if; 00420 00421 end if; 00422 end process; 00423 00424 00425 tlp_dw0 <= "0" & rx_tx_engine.request_reg_rd & "0010100" & rx_tx_engine.request_tc & "0000" & rx_tx_engine.request_attr & "0000" & "0000000" & rx_tx_engine.request_reg_rd; 00426 tlp_dw1 <= completer_id & cpl_status & '0' & cpl_byte_count; 00427 tlp_dw2 <= rx_tx_engine.request_id & rx_tx_engine.request_tag & '0' & rx_tx_engine.lower_adr & "00"; 00428 00429 cpl_byte_count <= "0000" & "0000" & "0" & rx_tx_engine.request_reg_rd & "00"; 00430 00431 reg_data <= reg_access_back.data after 1 ns when rising_edge( clk ) and reg_access_back.data_we='1'; 00432 tlp_dw3( 7 downto 0 ) <= reg_data( 31 downto 24 ); 00433 tlp_dw3( 15 downto 8 ) <= reg_data( 23 downto 16 ); 00434 tlp_dw3( 23 downto 16 ) <= reg_data( 15 downto 8 ); 00435 tlp_dw3( 31 downto 24 ) <= reg_data( 7 downto 0 ); 00436 00437 max_read_size <= x"20"; -- 128 байт 00438 read_tag <= "000" & req_cnt( 4 downto 0 ); 00439 00440 adr64 <= tx_ext_fifo_back.pci_adr( 39 ) or 00441 tx_ext_fifo_back.pci_adr( 38 ) or 00442 tx_ext_fifo_back.pci_adr( 37 ) or 00443 tx_ext_fifo_back.pci_adr( 36 ) or 00444 tx_ext_fifo_back.pci_adr( 35 ) or 00445 tx_ext_fifo_back.pci_adr( 34 ) or 00446 tx_ext_fifo_back.pci_adr( 33 ) or 00447 tx_ext_fifo_back.pci_adr( 32 ); 00448 00449 tlp_read_dw0 <= "00" & adr64 & '0' & x"000" & "00000000" & max_read_size; 00450 tlp_read_dw1 <= completer_id & read_tag & x"FF"; 00451 tlp_read_dw2 <= x"000000" & tx_ext_fifo_back.pci_adr( 39 downto 32 ); 00452 tlp_read_dw3( 6 downto 0 ) <= "0000000"; 00453 tlp_read_dw3( 8 downto 7 ) <= req_cnt( 1 downto 0 ); 00454 tlp_read_dw3( 11 downto 9 ) <= req_cnt( 4 downto 2 ) when tx_ext_fifo_back.rd_size='1' 00455 else tx_ext_fifo_back.pci_adr( 11 downto 9 ); 00456 00457 tlp_read_dw3( 31 downto 12 ) <= tx_ext_fifo_back.pci_adr( 31 downto 12 ); 00458 00459 00460 --tlp_read_dw0 <= x"0000" & "00000000" & max_read_size; 00461 --tlp_read_dw1 <= completer_id & read_tag & x"FF"; 00462 -- 00463 --tlp_read_dw2( 6 downto 0 ) <= "0000000"; 00464 --tlp_read_dw2( 8 downto 7 ) <= req_cnt( 1 downto 0 ); 00465 --tlp_read_dw2( 11 downto 9 ) <= req_cnt( 4 downto 2 ) when tx_ext_fifo_back.rd_size='1' 00466 -- else tx_ext_fifo_back.pci_adr( 11 downto 9 ); 00467 -- 00468 --tlp_read_dw2( 31 downto 12 ) <= tx_ext_fifo_back.pci_adr( 31 downto 12 ); 00469 -- 00470 --tlp_read_dw3 <= (others=>'0'); 00471 00472 00473 00474 pr_req_cnt: process( clk ) begin 00475 if( rising_edge( clk ) ) then 00476 if( stp=s0 and wait_complete='0' ) then 00477 req_cnt <= (others=>'0') after 1 ns; 00478 elsif( stp=sr3 ) then 00479 req_cnt <= req_cnt + 1 after 1 ns; 00480 end if; 00481 end if; 00482 end process; 00483 00484 00485 00486 rstpz1 <= rstpz after 1 ns when rising_edge( clk ); 00487 timeout_st0 <= ( not rstpz ) and (rstpz1 or timeout_cnt_en ) after 1 ns when rising_edge( clk ); 00488 00489 xtcnt: srlc32e port map( q31=>timeout_cnt_en, clk=>clk, d =>timeout_st0, a =>"11111", ce=>'1' ); 00490 00491 pr_timeout_cnt: process( clk ) begin 00492 if( rising_edge( clk ) ) then 00493 if( wait_complete='0' ) then 00494 timeout_cnt <= (others=>'0') after 1 ns; 00495 elsif( timeout_cnt_en='1' ) then 00496 timeout_cnt <= timeout_cnt + 1 after 1 ns; 00497 end if; 00498 end if; 00499 end process; 00500 00501 timeout_error <= timeout_cnt(10); 00502 00503 pr_complete_cnt: process( clk ) begin 00504 if( rising_edge( clk ) ) then 00505 if( wait_complete='0' ) then 00506 if( tx_ext_fifo_back.rd_size='0' ) then 00507 complete_cnt <= "0111000000" after 1 ns; -- 513-64 -- ожидается 512 байт 00508 else 00509 complete_cnt <= "0000000000" after 1 ns; -- ожидается 4096 байт (512 слов по 8 байт) 00510 end if; 00511 elsif( rx_tx_engine.complete_we='1' ) then 00512 complete_cnt <= complete_cnt + 1 after 1 ns; 00513 end if; 00514 end if; 00515 end process; 00516 00517 req_complete <= complete_cnt(9); 00518 00519 write_size <= trn_tx_back.cfg_dcommand(5); 00520 00521 pr_write_cnt: process( clk ) begin 00522 if( rising_edge( clk ) ) then 00523 if( stp=s0 ) then 00524 write_cnt <= '0' & not write_size & "000" & adr64 after 1 ns; 00525 elsif( write_cnt_en='1' ) then 00526 write_cnt <= write_cnt + 1 after 1 ns; 00527 end if; 00528 end if; 00529 end process; 00530 00531 write_cnt_eq <= write_cnt(5); 00532 00533 write_cnt_pkg_add <= write_size & not write_size; 00534 00535 pr_write_cnt_pkg: process( clk ) begin 00536 if( rising_edge( clk ) ) then 00537 if( stp=s0 and write_state='0' ) then 00538 write_cnt_pkg <= "00000" after 1 ns; 00539 elsif( stp=sw5 ) then 00540 write_cnt_pkg <= write_cnt_pkg + write_cnt_pkg_add after 1 ns; 00541 end if; 00542 end if; 00543 end process; 00544 00545 write_cnt_pkg_eq <= write_cnt_pkg(4) and write_cnt_pkg(3) and write_cnt_pkg(2) and write_cnt_pkg(1) and (write_cnt_pkg(0) or write_size); 00546 00547 00548 tlp_write_dw0 <= "01" & adr64 & '0' & x"000" & "00000000" & "0" & write_size & not write_size & "00000"; 00549 tlp_write_dw1 <= tlp_read_dw1; 00550 tlp_write_dw2 <= tlp_read_dw2; --x"000000" & tx_ext_fifo_back.pci_adr( 39 downto 32 ); 00551 tlp_write_dw3( 6 downto 0 ) <= "0000000"; 00552 tlp_write_dw3( 11 downto 7 ) <= write_cnt_pkg( 4 downto 0 ); 00553 tlp_write_dw3( 31 downto 12 ) <= tx_ext_fifo_back.pci_adr( 31 downto 12 ); 00554 00555 00556 --tlp_write_data <= x"00000000" & x"0000" & "0000000000" & write_cnt; 00557 gen_repack: for ii in 0 to 7 generate 00558 tlp_write_data( ii*8+7 downto ii*8 ) <= tx_ext_fifo_back.data( (7-ii)*8+7 downto (7-ii)*8 ); 00559 end generate; 00560 00561 tlp_write_data_z <= tlp_write_data( 31 downto 0 ) after 1 ns when rising_edge( clk ); 00562 00563 pr_adr_cnt: process( clk ) begin 00564 if( rising_edge( clk ) ) then 00565 if( write_cnt_en='0' ) then 00566 adr_cnt <= (others=>'0') after 1 ns; 00567 else 00568 adr_cnt <= adr_cnt + 1 after 1 ns; 00569 end if; 00570 end if; 00571 end process; 00572 00573 tx_ext_fifo.adr( 3 downto 0 ) <= adr_cnt( 3 downto 0 ); 00574 tx_ext_fifo.adr( 4 ) <= adr_cnt(4) or write_cnt_pkg(0); 00575 tx_ext_fifo.adr( 8 downto 5 ) <= write_cnt_pkg( 4 downto 1 ); 00576 00577 end core64_tx_engine;
1.7.4