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DS_DMA
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00001 ------------------------------------------------------------------------------- 00002 -- 00003 -- Title : core64_tx_engine_m4 00004 -- Author : Dmitry Smekhov 00005 -- Company : Instrumental Systems 00006 -- E-mail : dsmv@insys.ru 00007 -- 00008 -- Version : 1.0 00009 -- 00010 ------------------------------------------------------------------------------- 00011 -- 00012 -- Description : Формирователь пакетов 00013 -- Модификация 4 - Spartan-6 00014 -- 00015 ------------------------------------------------------------------------------- 00016 00017 library ieee; 00018 use ieee.std_logic_1164.all; 00019 00020 use work.core64_type_pkg.all; 00021 00022 package core64_tx_engine_m4_pkg is 00023 00024 component core64_tx_engine_m4 is 00025 port( 00026 00027 --- General --- 00028 rstp : in std_logic; --! 1 - сброс 00029 clk : in std_logic; --! тактовая частота ядра - 250 MHz 00030 00031 trn_tx : out type_trn_tx; --! передача пакета 00032 trn_tx_back : in type_trn_tx_back; --! готовность к передаче пакета 00033 00034 completer_id : in std_logic_vector( 15 downto 0 ); --! идентификатор устройства 00035 00036 reg_access_back : in type_reg_access_back; --! запрос на доступ к регистрам 00037 00038 rx_tx_engine : in type_rx_tx_engine; --! обмен RX->TX 00039 tx_rx_engine : out type_tx_rx_engine; --! обмен TX->RX 00040 00041 tx_ext_fifo : out type_tx_ext_fifo; --! обмен TX->EXT_FIFO 00042 tx_ext_fifo_back: in type_tx_ext_fifo_back --! обмен TX->EXT_FIFO 00043 00044 ); 00045 end component; 00046 00047 end package; 00048 00049 library ieee; 00050 use ieee.std_logic_1164.all; 00051 use ieee.std_logic_arith.all; 00052 use ieee.std_logic_unsigned.all; 00053 00054 use work.core64_type_pkg.all; 00055 00056 library unisim; 00057 use unisim.vcomponents.all; 00058 00059 entity core64_tx_engine_m4 is 00060 port( 00061 00062 --- General --- 00063 rstp : in std_logic; --! 1 - сброс 00064 clk : in std_logic; --! тактовая частота ядра - 250 MHz 00065 00066 trn_tx : out type_trn_tx; --! передача пакета 00067 trn_tx_back : in type_trn_tx_back; --! готовность к передаче пакета 00068 00069 completer_id : in std_logic_vector( 15 downto 0 ); --! идентификатор устройства 00070 00071 reg_access_back : in type_reg_access_back; --! запрос на доступ к регистрам 00072 00073 rx_tx_engine : in type_rx_tx_engine; --! обмен RX->TX 00074 tx_rx_engine : out type_tx_rx_engine; --! обмен TX->RX 00075 00076 tx_ext_fifo : out type_tx_ext_fifo; --! обмен TX->EXT_FIFO 00077 tx_ext_fifo_back: in type_tx_ext_fifo_back --! обмен TX->EXT_FIFO 00078 00079 ); 00080 end core64_tx_engine_m4; 00081 00082 00083 architecture core64_tx_engine_m4 of core64_tx_engine_m4 is 00084 00085 component ctrl_fifo64x34fw is 00086 port ( 00087 clk : in std_logic; 00088 rst : in std_logic; 00089 din : in std_logic_vector(33 downto 0); 00090 wr_en : in std_logic; 00091 rd_en : in std_logic; 00092 dout : out std_logic_vector(33 downto 0); 00093 full : out std_logic; 00094 empty : out std_logic; 00095 valid : out std_logic; 00096 prog_full : out std_logic; 00097 prog_empty : out std_logic 00098 ); 00099 end component; 00100 00101 00102 function set_data( data_in : in std_logic_vector( 31 downto 0 ) ) return std_logic_vector is 00103 00104 variable ret : std_logic_vector( 31 downto 0 ); 00105 00106 begin 00107 00108 for ii in 0 to 31 loop 00109 if( data_in(ii)='1' ) then 00110 ret(ii):='1'; 00111 else 00112 ret(ii):='0'; 00113 end if; 00114 end loop; 00115 00116 return ret; 00117 00118 end set_data; 00119 00120 signal rstpz : std_logic; 00121 00122 type stp_type is ( s0, s1, s2, s21, s3, s31, s4, sr1, sr2, sr21, sr22, sr3, sr4, sr5, 00123 sw1, sw01, sw02, sw04, sw2, sw30, sw31, sw5, sw6 ); 00124 signal stp : stp_type; 00125 00126 signal fifo_din : std_logic_vector( 33 downto 0 ); 00127 signal fifo_wr : std_logic; 00128 signal fifo_rd : std_logic; 00129 signal fifo_dout : std_logic_vector( 33 downto 0 ); 00130 signal fifo_full : std_logic; 00131 signal fifo_empty : std_logic; 00132 signal fifo_valid : std_logic; 00133 signal fifo_paf : std_logic; 00134 signal fifo_pae : std_logic; 00135 00136 signal fifo_sof : std_logic; 00137 signal fifo_eof : std_logic; 00138 signal fifo_rrem : std_logic; 00139 signal fifo_data : std_logic_vector( 31 downto 0 ); 00140 signal reg_data : std_logic_vector( 31 downto 0 ); 00141 signal tlp_dw0 : std_logic_vector( 31 downto 0 ); 00142 signal tlp_dw1 : std_logic_vector( 31 downto 0 ); 00143 signal tlp_dw2 : std_logic_vector( 31 downto 0 ); 00144 signal tlp_dw3 : std_logic_vector( 31 downto 0 ); 00145 00146 signal cpl_status : std_logic_vector( 2 downto 0 ):="000"; 00147 signal cpl_byte_count : std_logic_vector( 11 downto 0 ) :=x"000"; 00148 00149 signal tlp_read_dw0 : std_logic_vector( 31 downto 0 ); 00150 signal tlp_read_dw1 : std_logic_vector( 31 downto 0 ); 00151 signal tlp_read_dw2 : std_logic_vector( 31 downto 0 ); 00152 signal tlp_read_dw3 : std_logic_vector( 31 downto 0 ); 00153 00154 signal max_read_size : std_logic_vector( 7 downto 0 ); 00155 signal read_tag : std_logic_vector( 7 downto 0 ); 00156 00157 signal req_cnt : std_logic_vector( 5 downto 0 ); --! счётчик запросов 00158 signal req_complete : std_logic; --! 1 - получены все ответы 00159 00160 signal wait_complete : std_logic; 00161 00162 signal complete_cnt : std_logic_vector( 9 downto 0 ); --! счётчик принятых слов 00163 signal timeout_cnt : std_logic_vector( 10 downto 0 ); --! ожидание ответа 00164 signal timeout_cnt_en : std_logic; 00165 signal timeout_error : std_logic; 00166 signal timeout_st0 : std_logic; 00167 signal rstpz1 : std_logic; 00168 00169 signal write_cnt_en : std_logic; 00170 signal write_cnt : std_logic_vector( 5 downto 0 ); --! счётчик слов в пакете 00171 signal write_cnt_pkg : std_logic_vector( 4 downto 0 ); --! счётчик пакетов 00172 signal write_cnt_eq : std_logic; 00173 signal write_cnt_pkg_eq: std_logic; 00174 signal write_state : std_logic; 00175 signal write_size : std_logic; --! 1 - пакет 256 байт, 0 - пакет 128 байт 00176 signal write_cnt_pkg_add : std_logic_vector( 1 downto 0 ); 00177 00178 signal tlp_write_dw0 : std_logic_vector( 31 downto 0 ); 00179 signal tlp_write_dw1 : std_logic_vector( 31 downto 0 ); 00180 signal tlp_write_dw2 : std_logic_vector( 31 downto 0 ); 00181 signal tlp_write_dw3 : std_logic_vector( 31 downto 0 ); 00182 00183 signal tlp_write_data : std_logic_vector( 63 downto 0 ); 00184 signal tlp_write_data_z: std_logic_vector( 31 downto 0 ); 00185 signal adr_cnt : std_logic_vector( 5 downto 0 ); 00186 00187 signal adr64 : std_logic; 00188 signal allow_cpl : std_logic; 00189 signal allow_wr : std_logic; 00190 signal tbuf_av : std_logic_vector( 5 downto 0 ); 00191 signal write_cnt_en_z : std_logic; 00192 00193 begin 00194 00195 trn_tx.trn_td( 31 downto 0 ) <= fifo_dout( 31 downto 0 ); 00196 trn_tx.trn_tsof_n <= fifo_dout( 32 ); 00197 trn_tx.trn_teof_n <= fifo_dout( 33 ); 00198 --trn_tx.trn_trem_n( 7 downto 4 ) <= "0000"; 00199 --trn_tx.trn_trem_n( 3 downto 0 ) <= (others=>fifo_dout( 66 ) ); 00200 00201 trn_tx.trn_tsrc_dsc_n <= '1'; 00202 trn_tx.trn_terrfwd_n <= '1'; 00203 00204 trn_tx.trn_tsrc_rdy_n <= fifo_empty or trn_tx_back.trn_tdst_rdy_n; 00205 fifo_rd <= not ( fifo_empty or trn_tx_back.trn_tdst_rdy_n ); 00206 00207 fifo0_reg: ctrl_fifo64x34fw 00208 port map( 00209 clk => clk, 00210 rst => rstpz, 00211 din => fifo_din, 00212 wr_en => fifo_wr , 00213 rd_en => fifo_rd , 00214 dout => fifo_dout, 00215 full => fifo_full, 00216 empty => fifo_empty, 00217 valid => fifo_valid, 00218 prog_full => fifo_paf, 00219 prog_empty => fifo_pae 00220 ); 00221 00222 rstpz <= rstp after 1 ns when rising_edge( clk ); 00223 00224 fifo_din <= fifo_eof & fifo_sof & set_data( fifo_data ); 00225 00226 00227 tbuf_av <= trn_tx_back.trn_tbuf_av; 00228 00229 allow_cpl <= tbuf_av(4) or tbuf_av(3) or tbuf_av(2) or tbuf_av(1) or tbuf_av(0) after 1 ns when rising_edge( clk ); 00230 allow_wr <= tbuf_av(4) or tbuf_av(3) or tbuf_av(2) after 1 ns when rising_edge( clk ); 00231 00232 00233 pr_state: process( clk ) begin 00234 if( rising_edge( clk ) ) then 00235 00236 case( stp ) is 00237 when s0 => 00238 00239 if( fifo_paf='0' ) then 00240 00241 if( (rx_tx_engine.request_reg_wr='1' or rx_tx_engine.request_reg_rd='1') and allow_cpl='1' ) then 00242 stp <= s1 after 1 ns; 00243 elsif( tx_ext_fifo_back.req_rd='1' and allow_wr='1' ) then 00244 stp <= sr1 after 1 ns; 00245 elsif( tx_ext_fifo_back.req_wr='1' and allow_wr='1' ) then 00246 stp <= sw1 after 1 ns; 00247 end if; 00248 00249 end if; 00250 fifo_wr <= '0'; 00251 tx_rx_engine.complete_reg <= '0' after 1 ns; 00252 tx_ext_fifo.complete_ok <= '0' after 1 ns; 00253 tx_ext_fifo.complete_error <= '0' after 1 ns; 00254 write_cnt_en <= '0' after 1 ns; 00255 00256 00257 when s1 => 00258 if( reg_access_back.complete='1' ) then 00259 if( rx_tx_engine.request_reg_wr='1' ) then 00260 stp <= s4 after 1 ns; -- не отправляется при операции записи 00261 else 00262 stp <= s2 after 1 ns; 00263 end if; 00264 end if; 00265 00266 when s2 => 00267 fifo_sof <= '0' after 1 ns; 00268 fifo_eof <= '1' after 1 ns; 00269 fifo_data <= tlp_dw0 after 1 ns; 00270 fifo_wr <= '1' after 1 ns; 00271 stp <= s21 after 1 ns; 00272 00273 when s21 => 00274 fifo_sof <= '1' after 1 ns; 00275 fifo_eof <= '1' after 1 ns; 00276 fifo_data <= tlp_dw1 after 1 ns; 00277 stp <= s3 after 1 ns; 00278 00279 when s3 => 00280 00281 fifo_data <= tlp_dw2 after 1 ns; 00282 stp <= s31 after 1 ns; 00283 00284 when s31 => 00285 00286 fifo_eof <= '0' after 1 ns; 00287 fifo_data <= tlp_dw3 after 1 ns; 00288 stp <= s4 after 1 ns; 00289 00290 when s4 => 00291 fifo_wr <= '0' after 1 ns; 00292 tx_rx_engine.complete_reg <= '1' after 1 ns; 00293 if( rx_tx_engine.request_reg_wr='0' and rx_tx_engine.request_reg_rd='0' ) then 00294 stp <= s0 after 1 ns; 00295 end if; 00296 00297 when sr1 => ---- Запрос на чтение данных из памяти ---- 00298 00299 if( req_cnt(5)='1' or (req_cnt(2)='1' and tx_ext_fifo_back.rd_size='0' ) ) then 00300 stp <= sr4 after 1 ns; 00301 else 00302 stp <= sr2 after 1 ns; 00303 end if; 00304 00305 when sr2 => 00306 wait_complete <= '1' after 1 ns; 00307 fifo_sof <= '0' after 1 ns; 00308 fifo_eof <= '1' after 1 ns; 00309 fifo_data <= tlp_read_dw0 after 1 ns; 00310 fifo_wr <= '1' after 1 ns; 00311 stp <= sr21 after 1 ns; 00312 00313 when sr21 => 00314 fifo_sof <= '1' after 1 ns; 00315 fifo_data <= tlp_read_dw1 after 1 ns; 00316 if( adr64='1' ) then 00317 stp <= sr22 after 1 ns; 00318 else 00319 stp <= sr3 after 1 ns; 00320 end if; 00321 00322 when sr22 => 00323 fifo_data <= tlp_read_dw2 after 1 ns; 00324 stp <= sr3 after 1 ns; 00325 00326 when sr3 => 00327 fifo_eof <= '0' after 1 ns; 00328 fifo_data <= tlp_read_dw3 after 1 ns; 00329 fifo_wr <= '1' after 1 ns; 00330 stp <= s0 after 1 ns; 00331 00332 -- when sr3 => ---- Ожидание завершения запроса ---- 00333 -- fifo_wr <= '0' after 1 ns; 00334 -- stp <= sr0 after 1 ns; 00335 00336 when sr4 => --- Проверка завершения запроса ---- 00337 if( req_complete='1' or timeout_error='1' ) then 00338 stp <= sr5 after 1 ns; 00339 else 00340 stp <= s0 after 1 ns; 00341 end if; 00342 00343 when sr5 => 00344 wait_complete <= '0' after 1 ns; 00345 tx_ext_fifo.complete_ok <= req_complete after 1 ns; 00346 tx_ext_fifo.complete_error <= timeout_error after 1 ns; 00347 if( tx_ext_fifo_back.req_rd='0' ) then 00348 stp <= s0 after 1 ns; 00349 end if; 00350 00351 00352 when sw1 => --- Запись 4 кБ --- 00353 00354 --write_cnt_en <= not adr64 after 1 ns; 00355 stp <= sw01 after 1 ns; 00356 00357 when sw01 => --- Запись 4 кБ --- 00358 00359 00360 write_state <= '1' after 1 ns; 00361 00362 00363 fifo_sof <= '0' after 1 ns; 00364 fifo_eof <= '1' after 1 ns; 00365 fifo_data <= tlp_write_dw0 after 1 ns; 00366 fifo_wr <= '1' after 1 ns; 00367 00368 stp <= sw02 after 1 ns; 00369 00370 when sw02 => 00371 00372 fifo_sof <= '1' after 1 ns; 00373 fifo_data <= tlp_write_dw1 after 1 ns; 00374 00375 00376 if( adr64='1' ) then 00377 stp <= sw04 after 1 ns; 00378 else 00379 stp <= sw2 after 1 ns; 00380 write_cnt_en <= '1' after 1 ns; 00381 00382 end if; 00383 00384 when sw04 => 00385 fifo_data <= tlp_write_dw2 after 1 ns; 00386 stp <= sw2 after 1 ns; 00387 write_cnt_en <= '1' after 1 ns; 00388 00389 00390 when sw2 => 00391 00392 00393 write_cnt_en <= '0' after 1 ns; 00394 fifo_data <= tlp_write_dw3 after 1 ns; 00395 00396 stp <= sw30 after 1 ns; 00397 00398 when sw30 => 00399 fifo_data <= tlp_write_data( 63 downto 32 ) after 1 ns; 00400 write_cnt_en <= '1' after 1 ns; 00401 if( write_cnt_eq='1' ) then 00402 stp <= sw5 after 1 ns; 00403 else 00404 stp <= sw31 after 1 ns; 00405 end if; 00406 00407 when sw31 => 00408 write_cnt_en <= '0' after 1 ns; 00409 fifo_wr <= '1' after 1 ns; 00410 fifo_data <= tlp_write_data( 31 downto 0 ) after 1 ns; 00411 stp <= sw30 after 1 ns; 00412 00413 when sw5 => 00414 fifo_data <= tlp_write_data( 31 downto 0 ) after 1 ns; 00415 fifo_eof <= '0' after 1 ns; 00416 write_cnt_en <= '0' after 1 ns; 00417 if( write_cnt_pkg_eq='1' ) then 00418 stp <= sw6 after 1 ns; 00419 else 00420 stp <= s0 after 1 ns; 00421 end if; 00422 00423 when sw6 => 00424 fifo_wr <= '0' after 1 ns; 00425 tx_ext_fifo.complete_ok <= '1' after 1 ns; 00426 tx_ext_fifo.complete_error <= '0' after 1 ns; 00427 write_state <= '0' after 1 ns; 00428 if( tx_ext_fifo_back.req_wr='0' ) then 00429 stp <= s0 after 1 ns; 00430 end if; 00431 00432 00433 00434 00435 00436 end case; 00437 00438 00439 00440 00441 00442 if( rstpz='1' ) then 00443 stp <= s0 after 1 ns; 00444 wait_complete <= '0' after 1 ns; 00445 write_state <= '0' after 1 ns; 00446 end if; 00447 00448 end if; 00449 end process; 00450 00451 00452 tlp_dw0 <= "0" & rx_tx_engine.request_reg_rd & "0010100" & rx_tx_engine.request_tc & "0000" & rx_tx_engine.request_attr & "0000" & "0000000" & rx_tx_engine.request_reg_rd; 00453 tlp_dw1 <= completer_id & cpl_status & '0' & cpl_byte_count; 00454 tlp_dw2 <= rx_tx_engine.request_id & rx_tx_engine.request_tag & '0' & rx_tx_engine.lower_adr & "00"; 00455 00456 cpl_byte_count <= "0000" & "0000" & "0" & rx_tx_engine.request_reg_rd & "00"; 00457 00458 reg_data <= reg_access_back.data after 1 ns when rising_edge( clk ) and reg_access_back.data_we='1'; 00459 tlp_dw3( 7 downto 0 ) <= reg_data( 31 downto 24 ); 00460 tlp_dw3( 15 downto 8 ) <= reg_data( 23 downto 16 ); 00461 tlp_dw3( 23 downto 16 ) <= reg_data( 15 downto 8 ); 00462 tlp_dw3( 31 downto 24 ) <= reg_data( 7 downto 0 ); 00463 00464 max_read_size <= x"20"; -- 128 байт 00465 read_tag <= "000" & req_cnt( 4 downto 0 ); 00466 00467 adr64 <= tx_ext_fifo_back.pci_adr( 39 ) or 00468 tx_ext_fifo_back.pci_adr( 38 ) or 00469 tx_ext_fifo_back.pci_adr( 37 ) or 00470 tx_ext_fifo_back.pci_adr( 36 ) or 00471 tx_ext_fifo_back.pci_adr( 35 ) or 00472 tx_ext_fifo_back.pci_adr( 34 ) or 00473 tx_ext_fifo_back.pci_adr( 33 ) or 00474 tx_ext_fifo_back.pci_adr( 32 ); 00475 00476 tlp_read_dw0 <= "00" & adr64 & '0' & x"000" & "00000000" & max_read_size; 00477 tlp_read_dw1 <= completer_id & read_tag & x"FF"; 00478 tlp_read_dw2 <= x"000000" & tx_ext_fifo_back.pci_adr( 39 downto 32 ); 00479 tlp_read_dw3( 6 downto 0 ) <= "0000000"; 00480 tlp_read_dw3( 8 downto 7 ) <= req_cnt( 1 downto 0 ); 00481 tlp_read_dw3( 11 downto 9 ) <= req_cnt( 4 downto 2 ) when tx_ext_fifo_back.rd_size='1' 00482 else tx_ext_fifo_back.pci_adr( 11 downto 9 ); 00483 00484 tlp_read_dw3( 31 downto 12 ) <= tx_ext_fifo_back.pci_adr( 31 downto 12 ); 00485 00486 00487 --tlp_read_dw0 <= x"0000" & "00000000" & max_read_size; 00488 --tlp_read_dw1 <= completer_id & read_tag & x"FF"; 00489 -- 00490 --tlp_read_dw2( 6 downto 0 ) <= "0000000"; 00491 --tlp_read_dw2( 8 downto 7 ) <= req_cnt( 1 downto 0 ); 00492 --tlp_read_dw2( 11 downto 9 ) <= req_cnt( 4 downto 2 ) when tx_ext_fifo_back.rd_size='1' 00493 -- else tx_ext_fifo_back.pci_adr( 11 downto 9 ); 00494 -- 00495 --tlp_read_dw2( 31 downto 12 ) <= tx_ext_fifo_back.pci_adr( 31 downto 12 ); 00496 -- 00497 --tlp_read_dw3 <= (others=>'0'); 00498 00499 00500 00501 pr_req_cnt: process( clk ) begin 00502 if( rising_edge( clk ) ) then 00503 if( stp=s0 and wait_complete='0' ) then 00504 req_cnt <= (others=>'0') after 1 ns; 00505 elsif( stp=sr3 ) then 00506 req_cnt <= req_cnt + 1 after 1 ns; 00507 end if; 00508 end if; 00509 end process; 00510 00511 00512 00513 rstpz1 <= rstpz after 1 ns when rising_edge( clk ); 00514 timeout_st0 <= ( not rstpz ) and (rstpz1 or timeout_cnt_en ) after 1 ns when rising_edge( clk ); 00515 00516 xtcnt: srlc32e port map( q31=>timeout_cnt_en, clk=>clk, d =>timeout_st0, a =>"11111", ce=>'1' ); 00517 00518 pr_timeout_cnt: process( clk ) begin 00519 if( rising_edge( clk ) ) then 00520 if( wait_complete='0' ) then 00521 timeout_cnt <= (others=>'0') after 1 ns; 00522 elsif( timeout_cnt_en='1' ) then 00523 timeout_cnt <= timeout_cnt + 1 after 1 ns; 00524 end if; 00525 end if; 00526 end process; 00527 00528 timeout_error <= timeout_cnt(10); 00529 00530 pr_complete_cnt: process( clk ) begin 00531 if( rising_edge( clk ) ) then 00532 if( wait_complete='0' ) then 00533 if( tx_ext_fifo_back.rd_size='0' ) then 00534 complete_cnt <= "0111000000" after 1 ns; -- 513-64 -- ожидается 512 байт 00535 else 00536 complete_cnt <= "0000000000" after 1 ns; -- ожидается 4096 байт (512 слов по 8 байт) 00537 end if; 00538 elsif( rx_tx_engine.complete_we='1' ) then 00539 complete_cnt <= complete_cnt + 1 after 1 ns; 00540 end if; 00541 end if; 00542 end process; 00543 00544 req_complete <= complete_cnt(9); 00545 00546 write_size <= trn_tx_back.cfg_dcommand(5); 00547 00548 pr_write_cnt: process( clk ) begin 00549 if( rising_edge( clk ) ) then 00550 if( stp=s0 ) then 00551 write_cnt <= '0' & not write_size & "000" & '0' after 1 ns; 00552 elsif( write_cnt_en='1' ) then 00553 write_cnt <= write_cnt + 1 after 1 ns; 00554 end if; 00555 end if; 00556 end process; 00557 00558 write_cnt_eq <= write_cnt(5); 00559 00560 write_cnt_pkg_add <= write_size & not write_size; 00561 00562 pr_write_cnt_pkg: process( clk ) begin 00563 if( rising_edge( clk ) ) then 00564 if( stp=s0 and write_state='0' ) then 00565 write_cnt_pkg <= "00000" after 1 ns; 00566 elsif( stp=sw5 ) then 00567 write_cnt_pkg <= write_cnt_pkg + write_cnt_pkg_add after 1 ns; 00568 end if; 00569 end if; 00570 end process; 00571 00572 write_cnt_pkg_eq <= write_cnt_pkg(4) and write_cnt_pkg(3) and write_cnt_pkg(2) and write_cnt_pkg(1) and (write_cnt_pkg(0) or write_size); 00573 00574 00575 tlp_write_dw0 <= "01" & adr64 & '0' & x"000" & "00000000" & "0" & write_size & not write_size & "00000"; 00576 tlp_write_dw1 <= tlp_read_dw1; 00577 tlp_write_dw2 <= tlp_read_dw2; --x"000000" & tx_ext_fifo_back.pci_adr( 39 downto 32 ); 00578 tlp_write_dw3( 6 downto 0 ) <= "0000000"; 00579 tlp_write_dw3( 11 downto 7 ) <= write_cnt_pkg( 4 downto 0 ); 00580 tlp_write_dw3( 31 downto 12 ) <= tx_ext_fifo_back.pci_adr( 31 downto 12 ); 00581 00582 00583 --tlp_write_data <= x"00000000" & x"0000" & "0000000000" & write_cnt; 00584 gen_repack: for ii in 0 to 7 generate 00585 tlp_write_data( ii*8+7 downto ii*8 ) <= tx_ext_fifo_back.data( (7-ii)*8+7 downto (7-ii)*8 ); 00586 end generate; 00587 00588 tlp_write_data_z <= tlp_write_data( 31 downto 0 ) after 1 ns when rising_edge( clk ); 00589 00590 write_cnt_en_z <= write_cnt_en after 1 ns when rising_edge( clk ); 00591 00592 pr_adr_cnt: process( clk ) begin 00593 if( rising_edge( clk ) ) then 00594 if( stp=s0 ) then 00595 adr_cnt <= (others=>'0') after 1 ns; 00596 elsif( write_cnt_en_z='1' ) then 00597 adr_cnt <= adr_cnt + 1 after 1 ns; 00598 end if; 00599 end if; 00600 end process; 00601 00602 tx_ext_fifo.adr( 3 downto 0 ) <= adr_cnt( 3 downto 0 ); 00603 tx_ext_fifo.adr( 4 ) <= adr_cnt(4) or write_cnt_pkg(0); 00604 tx_ext_fifo.adr( 8 downto 5 ) <= write_cnt_pkg( 4 downto 1 ); 00605 00606 end core64_tx_engine_m4;
1.7.4