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DS_DMA
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00001 -------------------------------------------------------------------------------- 00002 -- This file is owned and controlled by Xilinx and must be used -- 00003 -- solely for design, simulation, implementation and creation of -- 00004 -- design files limited to Xilinx devices or technologies. Use -- 00005 -- with non-Xilinx devices or technologies is expressly prohibited -- 00006 -- and immediately terminates your license. -- 00007 -- -- 00008 -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- 00009 -- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- 00010 -- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- 00011 -- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- 00012 -- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- 00013 -- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- 00014 -- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- 00015 -- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- 00016 -- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- 00017 -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- 00018 -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- 00019 -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- 00020 -- FOR A PARTICULAR PURPOSE. -- 00021 -- -- 00022 -- Xilinx products are not intended for use in life support -- 00023 -- appliances, devices, or systems. Use in such applications are -- 00024 -- expressly prohibited. -- 00025 -- -- 00026 -- (c) Copyright 1995-2011 Xilinx, Inc. -- 00027 -- All rights reserved. -- 00028 -------------------------------------------------------------------------------- 00029 -- You must compile the wrapper file ctrl_fifo64x70st.vhd when simulating 00030 -- the core, ctrl_fifo64x70st. When compiling the wrapper file, be sure to 00031 -- reference the XilinxCoreLib VHDL simulation library. For detailed 00032 -- instructions, please refer to the "CORE Generator Help". 00033 00034 -- The synthesis directives "translate_off/translate_on" specified 00035 -- below are supported by Xilinx, Mentor Graphics and Synplicity 00036 -- synthesis tools. Ensure they are correct for your synthesis tool(s). 00037 00038 LIBRARY ieee; 00039 USE ieee.std_logic_1164.ALL; 00040 -- synthesis translate_off 00041 LIBRARY XilinxCoreLib; 00042 -- synthesis translate_on 00043 ENTITY ctrl_fifo64x70st IS 00044 PORT ( 00045 clk : IN STD_LOGIC; 00046 rst : IN STD_LOGIC; 00047 din : IN STD_LOGIC_VECTOR(69 DOWNTO 0); 00048 wr_en : IN STD_LOGIC; 00049 rd_en : IN STD_LOGIC; 00050 dout : OUT STD_LOGIC_VECTOR(69 DOWNTO 0); 00051 full : OUT STD_LOGIC; 00052 empty : OUT STD_LOGIC; 00053 valid : OUT STD_LOGIC; 00054 prog_full : OUT STD_LOGIC; 00055 prog_empty : OUT STD_LOGIC 00056 ); 00057 END ctrl_fifo64x70st; 00058 00059 ARCHITECTURE ctrl_fifo64x70st_a OF ctrl_fifo64x70st IS 00060 -- synthesis translate_off 00061 COMPONENT wrapped_ctrl_fifo64x70st 00062 PORT ( 00063 clk : IN STD_LOGIC; 00064 rst : IN STD_LOGIC; 00065 din : IN STD_LOGIC_VECTOR(69 DOWNTO 0); 00066 wr_en : IN STD_LOGIC; 00067 rd_en : IN STD_LOGIC; 00068 dout : OUT STD_LOGIC_VECTOR(69 DOWNTO 0); 00069 full : OUT STD_LOGIC; 00070 empty : OUT STD_LOGIC; 00071 valid : OUT STD_LOGIC; 00072 prog_full : OUT STD_LOGIC; 00073 prog_empty : OUT STD_LOGIC 00074 ); 00075 END COMPONENT; 00076 00077 -- Configuration specification 00078 FOR ALL : wrapped_ctrl_fifo64x70st USE ENTITY XilinxCoreLib.fifo_generator_v8_1(behavioral) 00079 GENERIC MAP ( 00080 c_add_ngc_constraint => 0, 00081 c_application_type_axis => 0, 00082 c_application_type_rach => 0, 00083 c_application_type_rdch => 0, 00084 c_application_type_wach => 0, 00085 c_application_type_wdch => 0, 00086 c_application_type_wrch => 0, 00087 c_axi_addr_width => 32 , 00088 c_axi_aruser_width => 1, 00089 c_axi_awuser_width => 1, 00090 c_axi_buser_width => 1, 00091 c_axi_data_width => 64 , 00092 c_axi_id_width => 4, 00093 c_axi_ruser_width => 1, 00094 c_axi_type => 0, 00095 c_axi_wuser_width => 1, 00096 c_axis_tdata_width => 64 , 00097 c_axis_tdest_width => 4, 00098 c_axis_tid_width => 8, 00099 c_axis_tkeep_width => 4, 00100 c_axis_tstrb_width => 4, 00101 c_axis_tuser_width => 4, 00102 c_axis_type => 0, 00103 c_common_clock => 1, 00104 c_count_type => 0, 00105 c_data_count_width => 6, 00106 c_default_value => "BlankString", 00107 c_din_width => 70 , 00108 c_din_width_axis => 1, 00109 c_din_width_rach => 32 , 00110 c_din_width_rdch => 64, 00111 c_din_width_wach => 32, 00112 c_din_width_wdch => 64, 00113 c_din_width_wrch => 2, 00114 c_dout_rst_val => "0" , 00115 c_dout_width => 70, 00116 c_enable_rlocs => 0, 00117 c_enable_rst_sync => 1, 00118 c_error_injection_type => 0, 00119 c_error_injection_type_axis => 0, 00120 c_error_injection_type_rach => 0, 00121 c_error_injection_type_rdch => 0, 00122 c_error_injection_type_wach => 0, 00123 c_error_injection_type_wdch => 0, 00124 c_error_injection_type_wrch => 0, 00125 c_family => "virtex5", 00126 c_full_flags_rst_val => 0, 00127 c_has_almost_empty => 0, 00128 c_has_almost_full => 0, 00129 c_has_axi_aruser => 0, 00130 c_has_axi_awuser => 0, 00131 c_has_axi_buser => 0, 00132 c_has_axi_rd_channel => 0, 00133 c_has_axi_ruser => 0, 00134 c_has_axi_wr_channel => 0, 00135 c_has_axi_wuser => 0, 00136 c_has_axis_tdata => 0, 00137 c_has_axis_tdest => 0, 00138 c_has_axis_tid => 0, 00139 c_has_axis_tkeep => 0, 00140 c_has_axis_tlast => 0, 00141 c_has_axis_tready => 1, 00142 c_has_axis_tstrb => 0, 00143 c_has_axis_tuser => 0, 00144 c_has_backup => 0, 00145 c_has_data_count => 0, 00146 c_has_data_counts_axis => 0, 00147 c_has_data_counts_rach => 0, 00148 c_has_data_counts_rdch => 0, 00149 c_has_data_counts_wach => 0, 00150 c_has_data_counts_wdch => 0, 00151 c_has_data_counts_wrch => 0, 00152 c_has_int_clk => 0, 00153 c_has_master_ce => 0, 00154 c_has_meminit_file => 0, 00155 c_has_overflow => 0, 00156 c_has_prog_flags_axis => 0, 00157 c_has_prog_flags_rach => 0, 00158 c_has_prog_flags_rdch => 0, 00159 c_has_prog_flags_wach => 0, 00160 c_has_prog_flags_wdch => 0, 00161 c_has_prog_flags_wrch => 0, 00162 c_has_rd_data_count => 0, 00163 c_has_rd_rst => 0, 00164 c_has_rst => 1, 00165 c_has_slave_ce => 0, 00166 c_has_srst => 0, 00167 c_has_underflow => 0, 00168 c_has_valid => 1, 00169 c_has_wr_ack => 0, 00170 c_has_wr_data_count => 0, 00171 c_has_wr_rst => 0, 00172 c_implementation_type => 0, 00173 c_implementation_type_axis => 1, 00174 c_implementation_type_rach => 1, 00175 c_implementation_type_rdch => 1, 00176 c_implementation_type_wach => 1, 00177 c_implementation_type_wdch => 1, 00178 c_implementation_type_wrch => 1, 00179 c_init_wr_pntr_val => 0, 00180 c_interface_type => 0, 00181 c_memory_type => 2, 00182 c_mif_file_name => "BlankString", 00183 c_msgon_val => 0, 00184 c_optimization_mode => 0, 00185 c_overflow_low => 0, 00186 c_preload_latency => 1, 00187 c_preload_regs => 0, 00188 c_prim_fifo_type => "512x72", 00189 c_prog_empty_thresh_assert_val => 2, 00190 c_prog_empty_thresh_assert_val_axis => 1022, 00191 c_prog_empty_thresh_assert_val_rach => 1022, 00192 c_prog_empty_thresh_assert_val_rdch => 1022, 00193 c_prog_empty_thresh_assert_val_wach => 1022, 00194 c_prog_empty_thresh_assert_val_wdch => 1022, 00195 c_prog_empty_thresh_assert_val_wrch => 1022, 00196 c_prog_empty_thresh_negate_val => 3, 00197 c_prog_empty_type => 1, 00198 c_prog_empty_type_axis => 5, 00199 c_prog_empty_type_rach => 5, 00200 c_prog_empty_type_rdch => 5, 00201 c_prog_empty_type_wach => 5, 00202 c_prog_empty_type_wdch => 5, 00203 c_prog_empty_type_wrch => 5, 00204 c_prog_full_thresh_assert_val => 56 , 00205 c_prog_full_thresh_assert_val_axis => 1023, 00206 c_prog_full_thresh_assert_val_rach => 1023, 00207 c_prog_full_thresh_assert_val_rdch => 1023, 00208 c_prog_full_thresh_assert_val_wach => 1023, 00209 c_prog_full_thresh_assert_val_wdch => 1023, 00210 c_prog_full_thresh_assert_val_wrch => 1023, 00211 c_prog_full_thresh_negate_val => 55, 00212 c_prog_full_type => 1, 00213 c_prog_full_type_axis => 5, 00214 c_prog_full_type_rach => 5, 00215 c_prog_full_type_rdch => 5, 00216 c_prog_full_type_wach => 5, 00217 c_prog_full_type_wdch => 5, 00218 c_prog_full_type_wrch => 5, 00219 c_rach_type => 0, 00220 c_rd_data_count_width => 6, 00221 c_rd_depth => 64 , 00222 c_rd_freq => 1, 00223 c_rd_pntr_width => 6, 00224 c_rdch_type => 0, 00225 c_reg_slice_mode_axis => 0, 00226 c_reg_slice_mode_rach => 0, 00227 c_reg_slice_mode_rdch => 0, 00228 c_reg_slice_mode_wach => 0, 00229 c_reg_slice_mode_wdch => 0, 00230 c_reg_slice_mode_wrch => 0, 00231 c_underflow_low => 0, 00232 c_use_common_overflow => 0, 00233 c_use_common_underflow => 0, 00234 c_use_default_settings => 0, 00235 c_use_dout_rst => 1, 00236 c_use_ecc => 0, 00237 c_use_ecc_axis => 0, 00238 c_use_ecc_rach => 0, 00239 c_use_ecc_rdch => 0, 00240 c_use_ecc_wach => 0, 00241 c_use_ecc_wdch => 0, 00242 c_use_ecc_wrch => 0, 00243 c_use_embedded_reg => 0, 00244 c_use_fifo16_flags => 0, 00245 c_use_fwft_data_count => 0, 00246 c_valid_low => 0, 00247 c_wach_type => 0, 00248 c_wdch_type => 0, 00249 c_wr_ack_low => 0, 00250 c_wr_data_count_width => 6, 00251 c_wr_depth => 64 , 00252 c_wr_depth_axis => 1024, 00253 c_wr_depth_rach => 16, 00254 c_wr_depth_rdch => 1024, 00255 c_wr_depth_wach => 16, 00256 c_wr_depth_wdch => 1024, 00257 c_wr_depth_wrch => 16, 00258 c_wr_freq => 1, 00259 c_wr_pntr_width => 6, 00260 c_wr_pntr_width_axis => 10 , 00261 c_wr_pntr_width_rach => 4, 00262 c_wr_pntr_width_rdch => 10 , 00263 c_wr_pntr_width_wach => 4, 00264 c_wr_pntr_width_wdch => 10 , 00265 c_wr_pntr_width_wrch => 4, 00266 c_wr_response_latency => 1, 00267 c_wrch_type => 0 00268 ); 00269 -- synthesis translate_on 00270 BEGIN 00271 -- synthesis translate_off 00272 U0 : wrapped_ctrl_fifo64x70st 00273 PORT MAP ( 00274 clk => clk, 00275 rst => rst, 00276 din => din, 00277 wr_en => wr_en, 00278 rd_en => rd_en, 00279 dout => dout , 00280 full => full , 00281 empty => empty, 00282 valid => valid, 00283 prog_full => prog_full, 00284 prog_empty => prog_empty 00285 ); 00286 -- synthesis translate_on 00287 00288 END ctrl_fifo64x70st_a;
1.7.4