pcie_src/pcie_core64_m1/source_virtex6/pcie_reset_delay_v6.vhd

-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
-- Project    : Virtex-6 Integrated Block for PCI Express
-- File       : pcie_reset_delay_v6.vhd
-- Version    : 2.3
-- Description: sys_reset_n delay (20ms) for Virtex6 PCIe Block
--
--
--
--------------------------------------------------------------------------------

library ieee;
   use ieee.std_logic_1164.all;
   use ieee.std_logic_unsigned.all;

entity pcie_reset_delay_v6 is
   generic (
      
      PL_FAST_TRAIN                                : boolean := FALSE;
      REF_CLK_FREQ                                 : integer := 0               -- 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz
   );
   port (
      ref_clk                                      : in std_logic;
      sys_reset_n                                  : in std_logic;
      delayed_sys_reset_n                          : out std_logic
   );
end pcie_reset_delay_v6;

architecture v6_pcie of pcie_reset_delay_v6 is
   
   constant TCQ                                    : integer := 1;
      
  function t_bit(
    constant PL_FAST_TRAIN    : boolean;
    constant REF_CLK_FREQ     : integer)
    return integer is
     variable tbit_out : integer := 2;
  begin  -- t_bit

    if (PL_FAST_TRAIN) then
      tbit_out := 2;
    else
     if (REF_CLK_FREQ = 0) then
      tbit_out := 20;
     elsif (REF_CLK_FREQ = 1) then
      tbit_out := 20;
     else
      tbit_out := 21;
     end if;
    end if;
    return tbit_out;
  end t_bit;

   constant TBIT                                   : integer := t_bit(PL_FAST_TRAIN, REF_CLK_FREQ);

   signal reg_count_7_0                            : std_logic_vector(7 downto 0);
   signal reg_count_15_8                           : std_logic_vector(7 downto 0);
   signal reg_count_23_16                          : std_logic_vector(7 downto 0);
   signal concat_count                             : std_logic_vector(23 downto 0);

   -- X-HDL generated signals

   signal v6pcie1 : std_logic_vector(7 downto 0);
   signal v6pcie2 : std_logic_vector(7 downto 0);
   
   -- Declare intermediate signals for referenced outputs
   signal delayed_sys_reset_n_v6pcie0                  : std_logic;

begin
   -- Drive referenced outputs
   delayed_sys_reset_n <= delayed_sys_reset_n_v6pcie0;
   
   concat_count <= (reg_count_23_16 & reg_count_15_8 & reg_count_7_0);
   
   
   v6pcie1 <= reg_count_15_8 + "00000001" when (reg_count_7_0 = "11111111") else
              reg_count_15_8;

   v6pcie2 <= reg_count_23_16 + "00000001" when ((reg_count_15_8 = "11111111") and (reg_count_7_0 = "11111111")) else
              reg_count_23_16;

   process (ref_clk, sys_reset_n)
   begin
     if ((not(sys_reset_n)) = '1') then

        reg_count_7_0 <= "00000000" after (TCQ)*1 ps;
        reg_count_15_8 <= "00000000" after (TCQ)*1 ps;
        reg_count_23_16 <= "00000000" after (TCQ)*1 ps;

     elsif (ref_clk'event and ref_clk = '1') then

       if (delayed_sys_reset_n_v6pcie0 /= '1') then

         reg_count_7_0 <= reg_count_7_0 + "00000001" after (TCQ)*1 ps;
         reg_count_15_8 <= v6pcie1 after (TCQ)*1 ps;
         reg_count_23_16 <= v6pcie2 after (TCQ)*1 ps;

       end if;

     end if;
   end process;
   
   
   delayed_sys_reset_n_v6pcie0 <= concat_count(TBIT);
   
end v6_pcie;