Граф наследования:cl_test_generate:
Processes | |
| pr_cnt1 | ( di_clk ) |
| pr_cnt1_z | ( di_clk ) |
| pr_state | ( di_clk ) |
| pr_xcnt1 | ( di_clk ) |
| pr_xcnt2 | ( di_clk ) |
| pr_block_mode | ( di_clk ) |
| pr_block_rd | ( di_clk ) |
| pr_data_expect | ( di_clk ) |
Types | |
| stp_type | ( s0 , s1 , s2 , s3 ) |
Signals | |
| block_rd | std_logic_vector ( 31 downto 0 ) |
| data_expect | std_logic_vector ( 63 downto 0 ) |
| cnt1 | std_logic_vector ( 24 downto 0 ) |
| cnt1_z | std_logic |
| cnt1_eq | std_logic |
| rst | std_logic |
| data_en | std_logic |
| data_ex0 | std_logic_vector ( 63 downto 0 ) |
| data_ex1 | std_logic_vector ( 63 downto 0 ) |
| data_ex2 | std_logic_vector ( 63 downto 0 ) |
| data_ex3 | std_logic_vector ( 63 downto 0 ) |
| data_ex4 | std_logic_vector ( 63 downto 0 ) |
| data_ex5 | std_logic_vector ( 63 downto 0 ) |
| block_mode | std_logic_vector ( 3 downto 0 ) |
| xcnt1 | std_logic_vector ( 15 downto 0 ) |
| xcnt2 | std_logic_vector ( 15 downto 0 ) |
| xcnt1_z | std_logic |
| xcnt2_z | std_logic |
| stp | stp_type |
| di_rdy | std_logic |
Подробное описание
См. определение в файле cl_test_generate.vhd строка 148
Объявления и описания членов класса находятся в файле:
- adm/main/cl_test_generate.vhd
