AMBPEX5_v20_SX50T_CORE
Ports | Libraries | Packages
trd_admdio64_out_v4 Entity Reference
Граф наследования:trd_admdio64_out_v4:
trd_admdio64_out_v4 ctrl_buft16 cl_chn_v4 cl_fifo1024x65_v5 ctrl_buft16 cl_chn_v4 cl_fifo1024x65_v5 ctrl_fifo1024x65_v5 cl_fifo_control_v2 ctrl_fifo1024x65_v5_a cl_fifo_control_v2 ambpex5_v20_sx50t_core trd_admdio64_out_v4_pkg ambpex5_v20_sx50t_core ambpex5_v20_sx50t_core_pkg stend_ambpex5_core stend_ambpex5_core_m2 stend_ambpex5_core stend_ambpex5_core_m2

Полный список членов класса



Architectures

trd_admdio64_out_v4  Architecture

Libraries

ieee 
unisim 
work 

Packages

std_logic_1164 
std_logic_unsigned 
vcomponents 
cl_chn_v4_pkg  Package <cl_chn_v4_pkg>
adm2_pkg  Package <adm2_pkg>
cl_fifo1024x65_v5_pkg  Package <cl_fifo1024x65_v5_pkg>

Ports

reset   in std_logic
clk   in std_logic
data_in   in std_logic_vector ( 63 downto 0 )
cmd_data_in   in std_logic_vector ( 15 downto 0 )
cmd   in bl_cmd
cmd_data_out   out std_logic_vector ( 15 downto 0 )
cmd_data_out2   out std_logic_vector ( 15 downto 0 )
bx_irq   out std_logic
bx_drq   out bl_drq
mode0   out std_logic_vector ( 15 downto 0 )
mode1   out std_logic_vector ( 15 downto 0 )
mode2   out std_logic_vector ( 15 downto 0 )
mode3   out std_logic_vector ( 15 downto 0 )
fifo_rst   out std_logic
start   out std_logic
data_out   out std_logic_vector ( 63 downto 0 )
data_cs   in std_logic
flag_rd   out bl_fifo_flag
clk_rd   in std_logic
fifo_cnt   out std_logic_vector ( 12 downto 0 )
test   out std_logic_vector ( 7 downto 0 )

Подробное описание

См. определение в файле trd_admdio64_out_v4.vhd строка 107


Объявления и описания членов класса находятся в файле: