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DS_DMA
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00001 ------------------------------------------------------------------------------- 00002 -- 00003 -- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved. 00004 -- 00005 -- This file contains confidential and proprietary information 00006 -- of Xilinx, Inc. and is protected under U.S. and 00007 -- international copyright and other intellectual property 00008 -- laws. 00009 -- 00010 -- DISCLAIMER 00011 -- This disclaimer is not a license and does not grant any 00012 -- rights to the materials distributed herewith. Except as 00013 -- otherwise provided in a valid license issued to you by 00014 -- Xilinx, and to the maximum extent permitted by applicable 00015 -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 00016 -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 00017 -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 00018 -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 00019 -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 00020 -- (2) Xilinx shall not be liable (whether in contract or tort, 00021 -- including negligence, or under any other theory of 00022 -- liability) for any loss or damage of any kind or nature 00023 -- related to, arising under or in connection with these 00024 -- materials, including for any direct, or any indirect, 00025 -- special, incidental, or consequential loss or damage 00026 -- (including loss of data, profits, goodwill, or any type of 00027 -- loss or damage suffered as a result of any action brought 00028 -- by a third party) even if such damage or loss was 00029 -- reasonably foreseeable or Xilinx had been advised of the 00030 -- possibility of the same. 00031 -- 00032 -- CRITICAL APPLICATIONS 00033 -- Xilinx products are not designed or intended to be fail- 00034 -- safe, or for use in any application requiring fail-safe 00035 -- performance, such as life-support or safety devices or 00036 -- systems, Class III medical devices, nuclear facilities, 00037 -- applications related to the deployment of airbags, or any 00038 -- other applications that could lead to death, personal 00039 -- injury, or severe property or environmental damage 00040 -- (individually and collectively, "Critical 00041 -- Applications"). Customer assumes the sole risk and 00042 -- liability of any use of Xilinx products in Critical 00043 -- Applications, subject only to applicable laws and 00044 -- regulations governing limitations on product liability. 00045 -- 00046 -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 00047 -- PART OF THIS FILE AT ALL TIMES. 00048 -- 00049 ------------------------------------------------------------------------------- 00050 -- Project : Virtex-6 Integrated Block for PCI Express 00051 -- File : axi_basic_rx.vhd 00052 -- Version : 2.3 00053 -- Description: 00054 -- TRN to AXI RX module. Instantiates pipeline and null generator RX 00055 -- submodules. 00056 -- 00057 -- Notes: 00058 -- Optional notes section. 00059 -- 00060 -- Hierarchical: 00061 -- axi_basic_top 00062 -- axi_basic_rx 00063 -------------------------------------------------------------------------------- 00064 -- Library Declarations 00065 -------------------------------------------------------------------------------- 00066 00067 LIBRARY ieee; 00068 USE ieee.std_logic_1164.all; 00069 USE ieee.std_logic_unsigned.all; 00070 00071 00072 ENTITY axi_basic_rx IS 00073 GENERIC ( 00074 C_DATA_WIDTH : INTEGER := 128; -- RX/TX interface data width 00075 C_FAMILY : STRING := "X7"; -- Targeted FPGA family 00076 C_ROOT_PORT : BOOLEAN := FALSE; -- PCIe block is in root port mode 00077 C_PM_PRIORITY : BOOLEAN := FALSE; -- Disable TX packet boundary thrtl 00078 TCQ : INTEGER := 1; -- Clock to Q time 00079 00080 C_REM_WIDTH : INTEGER := 1; -- trem/rrem width 00081 C_STRB_WIDTH : INTEGER := 4 -- TSTRB width 00082 ); 00083 PORT ( 00084 ------------------------------------------------- 00085 -- User Design I/O -- 00086 ------------------------------------------------- 00087 -- AXI RX 00088 ------------- 00089 00090 M_AXIS_RX_TDATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0):=(OTHERS=>'0'); -- RX data to user 00091 M_AXIS_RX_TVALID : OUT STD_LOGIC :='0'; -- RX data is valid 00092 M_AXIS_RX_TREADY : IN STD_LOGIC :='0'; -- RX ready for data 00093 M_AXIS_RX_TSTRB : OUT STD_LOGIC_VECTOR(C_STRB_WIDTH - 1 DOWNTO 0):=(OTHERS=>'0'); -- RX strobe byte enables 00094 M_AXIS_RX_TLAST : OUT STD_LOGIC :='0'; -- RX data is last 00095 M_AXIS_RX_TUSER : OUT STD_LOGIC_VECTOR(21 DOWNTO 0) :=(OTHERS=>'0'); -- RX user signals 00096 ------------------------------------------------- 00097 -- PCIe Block I/O -- 00098 ------------------------------------------------- 00099 -- TRN RX 00100 ------------- 00101 TRN_RD : IN STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) :=(OTHERS=>'0'); -- RX data from block 00102 TRN_RSOF : IN STD_LOGIC :='0'; -- RX start of packet 00103 TRN_REOF : IN STD_LOGIC :='0'; -- RX end of packet 00104 TRN_RSRC_RDY : IN STD_LOGIC :='0'; -- RX source ready 00105 TRN_RDST_RDY : OUT STD_LOGIC :='0'; -- RX destination ready 00106 TRN_RSRC_DSC : IN STD_LOGIC :='0'; -- RX source discontinue 00107 TRN_RREM : IN STD_LOGIC_VECTOR(C_REM_WIDTH - 1 DOWNTO 0) :=(OTHERS=>'0'); -- RX remainder 00108 TRN_RERRFWD : IN STD_LOGIC :='0'; -- RX error forward 00109 TRN_RBAR_HIT : IN STD_LOGIC_VECTOR(6 DOWNTO 0) :=(OTHERS=>'0'); -- RX BAR hit 00110 TRN_RECRC_ERR : IN STD_LOGIC :='0'; -- RX ECRC error 00111 00112 -- System 00113 ------------- 00114 NP_COUNTER : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) :=(OTHERS=>'0'); -- Non-posted counter 00115 USER_CLK : IN STD_LOGIC :='0'; -- user clock from block 00116 USER_RST : IN STD_LOGIC :='0' -- user reset from block 00117 ); 00118 END axi_basic_rx; 00119 00120 ------------------------------------------------- 00121 -- RX Data Pipeline -- 00122 ------------------------------------------------- 00123 00124 00125 ARCHITECTURE TRANS OF axi_basic_rx IS 00126 00127 SIGNAL null_rx_tvalid : STD_LOGIC; 00128 SIGNAL null_rx_tlast : STD_LOGIC; 00129 SIGNAL null_rx_tstrb : STD_LOGIC_VECTOR(C_STRB_WIDTH - 1 DOWNTO 0); 00130 SIGNAL null_rdst_rdy : STD_LOGIC; 00131 SIGNAL null_is_eof : STD_LOGIC_VECTOR(4 DOWNTO 0); 00132 00133 -- Declare intermediate signals for referenced outputs 00134 SIGNAL m_axis_rx_tdata_xhdl0 : STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0); 00135 SIGNAL m_axis_rx_tvalid_xhdl4 : STD_LOGIC; 00136 SIGNAL m_axis_rx_tstrb_xhdl2 : STD_LOGIC_VECTOR(C_STRB_WIDTH - 1 DOWNTO 0); 00137 SIGNAL m_axis_rx_tlast_xhdl1 : STD_LOGIC; 00138 SIGNAL m_axis_rx_tuser_xhdl3 : STD_LOGIC_VECTOR(21 DOWNTO 0); 00139 SIGNAL trn_rdst_rdy_xhdl6 : STD_LOGIC; 00140 SIGNAL np_counter_xhdl5 : STD_LOGIC_VECTOR(2 DOWNTO 0); 00141 00142 COMPONENT axi_basic_rx_null_gen IS 00143 GENERIC ( 00144 C_DATA_WIDTH : INTEGER := 128; 00145 TCQ : INTEGER := 1; 00146 C_STRB_WIDTH : INTEGER := 4 00147 ); 00148 PORT ( 00149 M_AXIS_RX_TDATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0'); 00150 M_AXIS_RX_TVALID : IN STD_LOGIC := '0'; 00151 M_AXIS_RX_TREADY : IN STD_LOGIC := '0'; 00152 M_AXIS_RX_TLAST : IN STD_LOGIC := '0'; 00153 M_AXIS_RX_TUSER : IN STD_LOGIC_VECTOR(21 DOWNTO 0) := (OTHERS=>'0'); 00154 00155 NULL_RX_TVALID : OUT STD_LOGIC := '0'; 00156 NULL_RX_TLAST : OUT STD_LOGIC := '0'; 00157 NULL_RX_TSTRB : OUT STD_LOGIC_VECTOR(C_STRB_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0'); 00158 NULL_RDST_RDY : OUT STD_LOGIC := '0'; 00159 NULL_IS_EOF : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS=>'0'); 00160 00161 USER_CLK : IN STD_LOGIC := '0'; 00162 USER_RST : IN STD_LOGIC := '0' 00163 ); 00164 END COMPONENT axi_basic_rx_null_gen; 00165 00166 ------------------------------------------------- 00167 -- RX Data Pipeline -- 00168 ------------------------------------------------- 00169 COMPONENT axi_basic_rx_pipeline IS 00170 GENERIC ( 00171 C_DATA_WIDTH : INTEGER := 128; 00172 C_FAMILY : STRING := "X7"; 00173 TCQ : INTEGER := 1; 00174 00175 C_REM_WIDTH : INTEGER := 1; 00176 C_STRB_WIDTH : INTEGER := 4 00177 ); 00178 PORT ( 00179 00180 M_AXIS_RX_TDATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0'); 00181 M_AXIS_RX_TVALID : OUT STD_LOGIC := '0'; 00182 M_AXIS_RX_TREADY : IN STD_LOGIC := '0'; 00183 M_AXIS_RX_TSTRB : OUT STD_LOGIC_VECTOR(C_STRB_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0'); 00184 M_AXIS_RX_TLAST : OUT STD_LOGIC := '0'; 00185 M_AXIS_RX_TUSER : OUT STD_LOGIC_VECTOR(21 DOWNTO 0) := (OTHERS=>'0'); 00186 00187 TRN_RD : IN STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0'); 00188 TRN_RSOF : IN STD_LOGIC := '0'; 00189 TRN_REOF : IN STD_LOGIC := '0'; 00190 TRN_RSRC_RDY : IN STD_LOGIC := '0'; 00191 TRN_RDST_RDY : OUT STD_LOGIC := '0'; 00192 TRN_RSRC_DSC : IN STD_LOGIC := '0'; 00193 TRN_RREM : IN STD_LOGIC_VECTOR(C_REM_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0'); 00194 TRN_RERRFWD : IN STD_LOGIC := '0'; 00195 TRN_RBAR_HIT : IN STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS=>'0'); 00196 TRN_RECRC_ERR : IN STD_LOGIC := '0'; 00197 00198 NULL_RX_TVALID : IN STD_LOGIC := '0'; 00199 NULL_RX_TLAST : IN STD_LOGIC := '0'; 00200 NULL_RX_TSTRB : IN STD_LOGIC_VECTOR(C_STRB_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0') ; 00201 NULL_RDST_RDY : IN STD_LOGIC := '0'; 00202 NULL_IS_EOF : IN STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS=>'0'); 00203 00204 NP_COUNTER : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) :=(OTHERS=>'0'); 00205 USER_CLK : IN STD_LOGIC :='0'; 00206 USER_RST : IN STD_LOGIC :='0' 00207 ); 00208 END COMPONENT axi_basic_rx_pipeline; 00209 BEGIN 00210 -- Drive referenced outputs 00211 M_AXIS_RX_TDATA <= m_axis_rx_tdata_xhdl0; 00212 M_AXIS_RX_TVALID <= m_axis_rx_tvalid_xhdl4; 00213 M_AXIS_RX_TSTRB <= m_axis_rx_tstrb_xhdl2; 00214 M_AXIS_RX_TLAST <= m_axis_rx_tlast_xhdl1; 00215 M_AXIS_RX_TUSER <= m_axis_rx_tuser_xhdl3; 00216 TRN_RDST_RDY <= trn_rdst_rdy_xhdl6; 00217 NP_COUNTER <= np_counter_xhdl5; 00218 00219 00220 rx_pipeline_inst : axi_basic_rx_pipeline 00221 GENERIC MAP ( 00222 C_DATA_WIDTH => C_DATA_WIDTH, 00223 C_FAMILY => C_FAMILY, 00224 TCQ => TCQ, 00225 C_REM_WIDTH => C_REM_WIDTH, 00226 C_STRB_WIDTH => C_STRB_WIDTH 00227 ) 00228 PORT MAP ( 00229 00230 ---------------------- 00231 -- Outgoing AXI TX 00232 ---------------------- 00233 M_AXIS_RX_TDATA => m_axis_rx_tdata_xhdl0, 00234 M_AXIS_RX_TVALID => m_axis_rx_tvalid_xhdl4, 00235 M_AXIS_RX_TREADY => M_AXIS_RX_TREADY, 00236 M_AXIS_RX_TSTRB => m_axis_rx_tstrb_xhdl2, 00237 M_AXIS_RX_TLAST => m_axis_rx_tlast_xhdl1, 00238 M_AXIS_RX_TUSER => m_axis_rx_tuser_xhdl3, 00239 00240 ---------------------- 00241 -- Incoming TRN RX 00242 ---------------------- 00243 TRN_RD => TRN_RD, 00244 TRN_RSOF => TRN_RSOF, 00245 TRN_REOF => TRN_REOF, 00246 TRN_RSRC_RDY => TRN_RSRC_RDY, 00247 TRN_RDST_RDY => trn_rdst_rdy_xhdl6, 00248 TRN_RSRC_DSC => TRN_RSRC_DSC, 00249 TRN_RREM => TRN_RREM, 00250 TRN_RERRFWD => TRN_RERRFWD, 00251 TRN_RBAR_HIT => TRN_RBAR_HIT, 00252 TRN_RECRC_ERR => TRN_RECRC_ERR, 00253 00254 ---------------------- 00255 -- Null Inputs 00256 ---------------------- 00257 NULL_RX_TVALID => null_rx_tvalid, 00258 NULL_RX_TLAST => null_rx_tlast, 00259 NULL_RX_TSTRB => null_rx_tstrb, 00260 NULL_RDST_RDY => null_rdst_rdy, 00261 NULL_IS_EOF => null_is_eof, 00262 00263 ---------------------- 00264 -- System 00265 ---------------------- 00266 NP_COUNTER => np_counter_xhdl5, 00267 USER_CLK => USER_CLK, 00268 USER_RST => USER_RST 00269 ); 00270 00271 00272 00273 rx_null_gen_inst : axi_basic_rx_null_gen 00274 GENERIC MAP ( 00275 C_DATA_WIDTH => C_DATA_WIDTH, 00276 TCQ => TCQ, 00277 C_STRB_WIDTH => C_STRB_WIDTH 00278 ) 00279 PORT MAP ( 00280 ---------------------- 00281 -- Inputs 00282 ---------------------- 00283 M_AXIS_RX_TDATA => m_axis_rx_tdata_xhdl0, 00284 M_AXIS_RX_TVALID => m_axis_rx_tvalid_xhdl4, 00285 M_AXIS_RX_TREADY => M_AXIS_RX_TREADY, 00286 M_AXIS_RX_TLAST => m_axis_rx_tlast_xhdl1, 00287 M_AXIS_RX_TUSER => m_axis_rx_tuser_xhdl3, 00288 00289 ---------------------- 00290 -- Null Outputs 00291 ---------------------- 00292 NULL_RX_TVALID => null_rx_tvalid, 00293 NULL_RX_TLAST => null_rx_tlast, 00294 NULL_RX_TSTRB => null_rx_tstrb, 00295 NULL_RDST_RDY => null_rdst_rdy, 00296 NULL_IS_EOF => null_is_eof, 00297 00298 ---------------------- 00299 -- System 00300 ---------------------- 00301 USER_CLK => USER_CLK, 00302 USER_RST => USER_RST 00303 ); 00304 00305 END TRANS;
1.7.4