axi_basic_tx_thrtl_ctl Entity Reference

Граф наследования:axi_basic_tx_thrtl_ctl:

Полный список членов класса

Architectures
trans	Architecture
Libraries
ieee
Packages
std_logic_1164
std_logic_unsigned
Generics
C_DATA_WIDTH	integer := 128
C_FAMILY	string := " x7 "
C_ROOT_PORT	boolean := false
TCQ	integer := 1
Ports
S_AXIS_TX_TDATA	in std_logic_vector ( c_data_width- 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS_TX_TVALID	in std_logic := ' 0 '
S_AXIS_TX_TUSER	in std_logic_vector ( 3 downto 0 ) := " 0000 "
S_AXIS_TX_TLAST	in std_logic := ' 0 '
USER_TURNOFF_OK	in std_logic := ' 0 '
USER_TCFG_GNT	in std_logic := ' 0 '
TRN_TBUF_AV	in std_logic_vector ( 5 downto 0 ) := " 000000 "
TRN_TDST_RDY	in std_logic := ' 0 '
TRN_TCFG_REQ	in std_logic := ' 0 '
TRN_TCFG_GNT	out std_logic
TRN_LNK_UP	in std_logic := ' 0 '
CFG_PCIE_LINK_STATE	in std_logic_vector ( 2 downto 0 ) := " 000 "
CFG_PM_SEND_PME_TO	in std_logic := ' 0 '
CFG_PMCSR_POWERSTATE	in std_logic_vector ( 1 downto 0 ) := " 00 "
TRN_RDLLP_DATA	in std_logic_vector ( 31 downto 0 ) := x " 00000000 "
TRN_RDLLP_SRC_RDY	in std_logic := ' 0 '
CFG_TO_TURNOFF	in std_logic := ' 0 '
CFG_TURNOFF_OK	out std_logic
TREADY_THRTL	out std_logic
USER_CLK	in std_logic := ' 0 '
USER_RST	in std_logic := ' 0 '

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Подробное описание

См. определение в файле axi_basic_tx_thrtl_ctl.vhd строка 74

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Объявления и описания членов класса находятся в файле:

• pcie_src/pcie_core64_m1/source_virtex6/axi_basic_tx_thrtl_ctl.vhd