DS_DMA
|
Processes | |
pr0_state | ( clk ) |
pr1_state | ( clk ) |
Types | |
stp_type | ( s0 , s1 , s2 ) |
Signals | |
bar0_complete | std_logic |
bar1_complete | std_logic |
adr | std_logic_vector ( 31 downto 0 ) |
bar0_write | std_logic |
bar0_read | std_logic |
bar1_read | std_logic |
bar0i_data | std_logic_vector ( 31 downto 0 ) |
bar0_data | std_logic_vector ( 31 downto 0 ) |
bar1_data | std_logic_vector ( 31 downto 0 ) |
stp | stp_type |
st1p | stp_type |
disp_complete | std_logic |
См. определение в файле core64_reg_access.vhd строка 102