Граф наследования:pcie_bram_top_s6:
Architectures | |
| rtl | Architecture |
Libraries | |
| ieee | |
Packages | |
| std_logic_1164 | |
| std_logic_arith | |
| std_logic_unsigned | |
Generics | |
| DEV_CAP_MAX_PAYLOAD_SUPPORTED | integer := 0 |
| VC0_TX_LASTPACKET | integer := 31 |
| TLM_TX_OVERHEAD | integer := 20 |
| TL_TX_RAM_RADDR_LATENCY | integer := 1 |
| TL_TX_RAM_RDATA_LATENCY | integer := 2 |
| TL_TX_RAM_WRITE_LATENCY | integer := 1 |
| VC0_RX_LIMIT | integer := 16#1fff# |
| TL_RX_RAM_RADDR_LATENCY | integer := 1 |
| TL_RX_RAM_RDATA_LATENCY | integer := 2 |
| TL_RX_RAM_WRITE_LATENCY | integer := 1 |
Ports | |
| user_clk_i | in std_logic |
| reset_i | in std_logic |
| mim_tx_wen | in std_logic |
| mim_tx_waddr | in std_logic_vector ( 11 downto 0 ) |
| mim_tx_wdata | in std_logic_vector ( 35 downto 0 ) |
| mim_tx_ren | in std_logic |
| mim_tx_rce | in std_logic |
| mim_tx_raddr | in std_logic_vector ( 11 downto 0 ) |
| mim_tx_rdata | out std_logic_vector ( 35 downto 0 ) |
| mim_rx_wen | in std_logic |
| mim_rx_waddr | in std_logic_vector ( 11 downto 0 ) |
| mim_rx_wdata | in std_logic_vector ( 35 downto 0 ) |
| mim_rx_ren | in std_logic |
| mim_rx_rce | in std_logic |
| mim_rx_raddr | in std_logic_vector ( 11 downto 0 ) |
| mim_rx_rdata | out std_logic_vector ( 35 downto 0 ) |
Подробное описание
См. определение в файле pcie_bram_top_s6.vhd строка 64
Объявления и описания членов класса находятся в файле:
- pcie_src/pcie_core64_m1/source_s6/pcie_bram_top_s6.vhd
