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DS_DMA
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00001 ------------------------------------------------------------------------------- 00002 -- 00003 -- Title : core64_tx_engine_m2 00004 -- Author : Dmitry Smekhov 00005 -- Company : Instrumental Systems 00006 -- E-mail : dsmv@insys.ru 00007 -- 00008 -- Version : 1.0 00009 -- 00010 ------------------------------------------------------------------------------- 00011 -- 00012 -- Description : Формирователь пакетов 00013 -- Модификация 2 - используется интерфейс AXI 00014 -- 00015 ------------------------------------------------------------------------------- 00016 -- 00017 -- Version 1.0 16.08.2011 00018 -- Создан из core64_tx_engine v1.0 00019 -- 00020 ------------------------------------------------------------------------------- 00021 00022 library ieee; 00023 use ieee.std_logic_1164.all; 00024 00025 use work.core64_type_pkg.all; 00026 00027 package core64_tx_engine_m2_pkg is 00028 00029 component core64_tx_engine_m2 is 00030 port( 00031 00032 --- General --- 00033 rstp : in std_logic; --! 1 - сброс 00034 clk : in std_logic; --! тактовая частота ядра - 250 MHz 00035 00036 trn_tx : out type_axi_tx; --! передача пакета 00037 trn_tx_back : in type_axi_tx_back; --! готовность к передаче пакета 00038 00039 completer_id : in std_logic_vector( 15 downto 0 ); --! идентификатор устройства 00040 00041 reg_access_back : in type_reg_access_back; --! запрос на доступ к регистрам 00042 00043 rx_tx_engine : in type_rx_tx_engine; --! обмен RX->TX 00044 tx_rx_engine : out type_tx_rx_engine; --! обмен TX->RX 00045 00046 tx_ext_fifo : out type_tx_ext_fifo; --! обмен TX->EXT_FIFO 00047 tx_ext_fifo_back: in type_tx_ext_fifo_back --! обмен TX->EXT_FIFO 00048 00049 ); 00050 end component; 00051 00052 end package; 00053 00054 library ieee; 00055 use ieee.std_logic_1164.all; 00056 use ieee.std_logic_arith.all; 00057 use ieee.std_logic_unsigned.all; 00058 00059 use work.core64_type_pkg.all; 00060 00061 library unisim; 00062 use unisim.vcomponents.all; 00063 00064 entity core64_tx_engine_m2 is 00065 port( 00066 00067 --- General --- 00068 rstp : in std_logic; --! 1 - сброс 00069 clk : in std_logic; --! тактовая частота ядра - 250 MHz 00070 00071 trn_tx : out type_axi_tx; --! передача пакета 00072 trn_tx_back : in type_axi_tx_back; --! готовность к передаче пакета 00073 00074 completer_id : in std_logic_vector( 15 downto 0 ); --! идентификатор устройства 00075 00076 reg_access_back : in type_reg_access_back; --! запрос на доступ к регистрам 00077 00078 rx_tx_engine : in type_rx_tx_engine; --! обмен RX->TX 00079 tx_rx_engine : out type_tx_rx_engine; --! обмен TX->RX 00080 00081 tx_ext_fifo : out type_tx_ext_fifo; --! обмен TX->EXT_FIFO 00082 tx_ext_fifo_back: in type_tx_ext_fifo_back --! обмен TX->EXT_FIFO 00083 00084 ); 00085 end core64_tx_engine_m2; 00086 00087 00088 architecture core64_tx_engine_m2 of core64_tx_engine_m2 is 00089 00090 component ctrl_fifo64x67fw is 00091 port ( 00092 clk : in std_logic; 00093 rst : in std_logic; 00094 din : in std_logic_vector(66 downto 0); 00095 wr_en : in std_logic; 00096 rd_en : in std_logic; 00097 dout : out std_logic_vector(66 downto 0); 00098 full : out std_logic; 00099 empty : out std_logic; 00100 valid : out std_logic; 00101 prog_full : out std_logic; 00102 prog_empty : out std_logic 00103 ); 00104 end component; 00105 00106 function set_data( data_in : in std_logic_vector( 63 downto 0 ) ) return std_logic_vector is 00107 00108 variable ret : std_logic_vector( 63 downto 0 ); 00109 00110 begin 00111 00112 for ii in 0 to 63 loop 00113 if( data_in(ii)='1' ) then 00114 ret(ii):='1'; 00115 else 00116 ret(ii):='0'; 00117 end if; 00118 end loop; 00119 00120 return ret; 00121 00122 end set_data; 00123 00124 signal rstpz : std_logic; 00125 00126 type stp_type is ( s0, s1, s2, s3, s4, sr1, sr2, sr3, sr4, sr5, 00127 sw1, sw01, sw2, sw3, sw5, sw6 ); 00128 signal stp : stp_type; 00129 00130 signal fifo_din : std_logic_vector( 66 downto 0 ); 00131 signal fifo_wr : std_logic; 00132 signal fifo_rd : std_logic; 00133 signal fifo_dout : std_logic_vector( 66 downto 0 ); 00134 signal fifo_full : std_logic; 00135 signal fifo_empty : std_logic; 00136 signal fifo_valid : std_logic; 00137 signal fifo_paf : std_logic; 00138 signal fifo_pae : std_logic; 00139 00140 signal fifo_sof : std_logic; 00141 signal fifo_eof : std_logic; 00142 signal fifo_rrem : std_logic; 00143 signal fifo_data : std_logic_vector( 63 downto 0 ); 00144 signal reg_data : std_logic_vector( 31 downto 0 ); 00145 signal tlp_dw0 : std_logic_vector( 31 downto 0 ); 00146 signal tlp_dw1 : std_logic_vector( 31 downto 0 ); 00147 signal tlp_dw2 : std_logic_vector( 31 downto 0 ); 00148 signal tlp_dw3 : std_logic_vector( 31 downto 0 ); 00149 00150 signal cpl_status : std_logic_vector( 2 downto 0 ):="000"; 00151 signal cpl_byte_count : std_logic_vector( 11 downto 0 ) :=x"000"; 00152 00153 signal tlp_read_dw0 : std_logic_vector( 31 downto 0 ); 00154 signal tlp_read_dw1 : std_logic_vector( 31 downto 0 ); 00155 signal tlp_read_dw2 : std_logic_vector( 31 downto 0 ); 00156 signal tlp_read_dw3 : std_logic_vector( 31 downto 0 ); 00157 00158 signal max_read_size : std_logic_vector( 7 downto 0 ); 00159 signal read_tag : std_logic_vector( 7 downto 0 ); 00160 00161 signal req_cnt : std_logic_vector( 5 downto 0 ); --! счётчик запросов 00162 signal req_complete : std_logic; --! 1 - получены все ответы 00163 00164 signal wait_complete : std_logic; 00165 00166 signal complete_cnt : std_logic_vector( 9 downto 0 ); --! счётчик принятых слов 00167 signal timeout_cnt : std_logic_vector( 10 downto 0 ); --! ожидание ответа 00168 signal timeout_cnt_en : std_logic; 00169 signal timeout_error : std_logic; 00170 signal timeout_st0 : std_logic; 00171 signal rstpz1 : std_logic; 00172 00173 signal write_cnt_en : std_logic; 00174 signal write_cnt : std_logic_vector( 5 downto 0 ); --! счётчик слов в пакете 00175 signal write_cnt_pkg : std_logic_vector( 4 downto 0 ); --! счётчик пакетов 00176 signal write_cnt_eq : std_logic; 00177 signal write_cnt_pkg_eq: std_logic; 00178 signal write_state : std_logic; 00179 signal write_size : std_logic; --! 1 - пакет 256 байт, 0 - пакет 128 байт 00180 signal write_cnt_pkg_add : std_logic_vector( 1 downto 0 ); 00181 00182 signal tlp_write_dw0 : std_logic_vector( 31 downto 0 ); 00183 signal tlp_write_dw1 : std_logic_vector( 31 downto 0 ); 00184 signal tlp_write_dw2 : std_logic_vector( 31 downto 0 ); 00185 signal tlp_write_dw3 : std_logic_vector( 31 downto 0 ); 00186 00187 signal tlp_write_data : std_logic_vector( 63 downto 0 ); 00188 signal tlp_write_data_z: std_logic_vector( 31 downto 0 ); 00189 signal adr_cnt : std_logic_vector( 5 downto 0 ); 00190 00191 signal adr64 : std_logic; 00192 signal axis_tx_tstrb_h : std_logic; 00193 00194 signal allow_wr : std_logic; 00195 signal allow_cpl : std_logic; 00196 signal tbuf_av : std_logic_vector( 5 downto 0 ); 00197 00198 begin 00199 00200 trn_tx.s_axis_tx_tdata <= fifo_dout( 31 downto 0 ) & fifo_dout( 63 downto 32 ); 00201 trn_tx.s_axis_tx_tstrb( 3 downto 0 ) <= "1111"; 00202 00203 axis_tx_tstrb_h <= fifo_dout( 65 ) or fifo_dout(66); 00204 trn_tx.s_axis_tx_tstrb( 7 downto 4 ) <= (others=> axis_tx_tstrb_h ); 00205 00206 trn_tx.s_axis_tx_tvalid <= fifo_valid; 00207 trn_tx.s_axis_tx_tlast <= not fifo_dout( 65 ); 00208 00209 00210 00211 trn_tx.s_axis_tx_tuser <= "0000"; 00212 00213 --trn_tx.trn_tsof_n <= fifo_dout( 64 ); 00214 --trn_tx.trn_teof_n <= fifo_dout( 65 ); 00215 --trn_tx.trn_trem_n( 7 downto 4 ) <= "0000"; 00216 --trn_tx.trn_trem_n( 3 downto 0 ) <= (others=>fifo_dout( 66 ) ); 00217 -- 00218 --trn_tx.trn_tsrc_dsc_n <= '1'; 00219 --trn_tx.trn_terrfwd_n <= '1'; 00220 -- 00221 --trn_tx.trn_tsrc_rdy_n <= fifo_empty or trn_tx_back.trn_tdst_rdy_n; 00222 fifo_rd <= (not fifo_empty) and trn_tx_back.s_axis_tx_tready; 00223 00224 fifo0_reg: ctrl_fifo64x67fw 00225 port map( 00226 clk => clk, 00227 rst => rstpz, 00228 din => fifo_din, 00229 wr_en => fifo_wr , 00230 rd_en => fifo_rd , 00231 dout => fifo_dout, 00232 full => fifo_full, 00233 empty => fifo_empty, 00234 valid => fifo_valid, 00235 prog_full => fifo_paf, 00236 prog_empty => fifo_pae 00237 ); 00238 00239 rstpz <= rstp after 1 ns when rising_edge( clk ); 00240 00241 fifo_din <= fifo_rrem & fifo_eof & fifo_sof & set_data( fifo_data ); 00242 00243 tbuf_av <= trn_tx_back.trn_tbuf_av; 00244 00245 allow_cpl <= tbuf_av(4) or tbuf_av(3) or tbuf_av(2) or tbuf_av(1) or tbuf_av(0) after 1 ns when rising_edge( clk ); 00246 allow_wr <= tbuf_av(4) or tbuf_av(3) or tbuf_av(2) after 1 ns when rising_edge( clk ); 00247 00248 00249 pr_state: process( clk ) begin 00250 if( rising_edge( clk ) ) then 00251 00252 case( stp ) is 00253 when s0 => 00254 00255 if( fifo_paf='0' ) then 00256 00257 if( (rx_tx_engine.request_reg_wr='1' or rx_tx_engine.request_reg_rd='1') and allow_cpl='1' ) then 00258 stp <= s1 after 1 ns; 00259 elsif( tx_ext_fifo_back.req_rd='1' and allow_wr='1' ) then 00260 stp <= sr1 after 1 ns; 00261 elsif( tx_ext_fifo_back.req_wr='1' and allow_wr='1' ) then 00262 stp <= sw1 after 1 ns; 00263 end if; 00264 00265 end if; 00266 fifo_wr <= '0'; 00267 tx_rx_engine.complete_reg <= '0' after 1 ns; 00268 tx_ext_fifo.complete_ok <= '0' after 1 ns; 00269 tx_ext_fifo.complete_error <= '0' after 1 ns; 00270 write_cnt_en <= '0' after 1 ns; 00271 00272 00273 when s1 => 00274 if( reg_access_back.complete='1' ) then 00275 if( rx_tx_engine.request_reg_wr='1' ) then 00276 stp <= s4 after 1 ns; -- не отправляется при операции записи 00277 else 00278 stp <= s2 after 1 ns; 00279 end if; 00280 end if; 00281 00282 when s2 => 00283 fifo_sof <= '0' after 1 ns; 00284 fifo_eof <= '1' after 1 ns; 00285 fifo_rrem <= '1' after 1 ns; 00286 fifo_data <= tlp_dw0 & tlp_dw1 after 1 ns; 00287 fifo_wr <= '1' after 1 ns; 00288 stp <= s3 after 1 ns; 00289 00290 when s3 => 00291 00292 fifo_sof <= '1' after 1 ns; 00293 fifo_eof <= '0' after 1 ns; 00294 fifo_rrem <= '1' after 1 ns; 00295 fifo_data <= tlp_dw2 & tlp_dw3 after 1 ns; 00296 fifo_wr <= '1' after 1 ns; 00297 stp <= s4 after 1 ns; 00298 00299 when s4 => 00300 fifo_wr <= '0' after 1 ns; 00301 tx_rx_engine.complete_reg <= '1' after 1 ns; 00302 if( rx_tx_engine.request_reg_wr='0' and rx_tx_engine.request_reg_rd='0' ) then 00303 stp <= s0 after 1 ns; 00304 end if; 00305 00306 when sr1 => ---- Запрос на чтение данных из памяти ---- 00307 00308 if( req_cnt(5)='1' or (req_cnt(2)='1' and tx_ext_fifo_back.rd_size='0' ) ) then 00309 stp <= sr4 after 1 ns; 00310 else 00311 stp <= sr2 after 1 ns; 00312 end if; 00313 00314 when sr2 => 00315 wait_complete <= '1' after 1 ns; 00316 fifo_sof <= '0' after 1 ns; 00317 fifo_eof <= '1' after 1 ns; 00318 fifo_rrem <= adr64 after 1 ns; 00319 fifo_data <= tlp_read_dw0 & tlp_read_dw1 after 1 ns; 00320 fifo_wr <= '1' after 1 ns; 00321 stp <= sr3 after 1 ns; 00322 00323 when sr3 => 00324 fifo_sof <= '1' after 1 ns; 00325 fifo_eof <= '0' after 1 ns; 00326 if( adr64='1' ) then 00327 fifo_data <= tlp_read_dw2 & tlp_read_dw3 after 1 ns; 00328 else 00329 fifo_data <= tlp_read_dw3 & tlp_read_dw3 after 1 ns; 00330 end if; 00331 00332 fifo_wr <= '1' after 1 ns; 00333 stp <= s0 after 1 ns; 00334 00335 -- when sr3 => ---- Ожидание завершения запроса ---- 00336 -- fifo_wr <= '0' after 1 ns; 00337 -- stp <= sr0 after 1 ns; 00338 00339 when sr4 => --- Проверка завершения запроса ---- 00340 if( req_complete='1' or timeout_error='1' ) then 00341 stp <= sr5 after 1 ns; 00342 else 00343 stp <= s0 after 1 ns; 00344 end if; 00345 00346 when sr5 => 00347 wait_complete <= '0' after 1 ns; 00348 tx_ext_fifo.complete_ok <= req_complete after 1 ns; 00349 tx_ext_fifo.complete_error <= timeout_error after 1 ns; 00350 if( tx_ext_fifo_back.req_rd='0' ) then 00351 stp <= s0 after 1 ns; 00352 end if; 00353 00354 00355 when sw1 => --- Запись 4 кБ --- 00356 00357 write_cnt_en <= not adr64 after 1 ns; 00358 stp <= sw01 after 1 ns; 00359 00360 when sw01 => --- Запись 4 кБ --- 00361 00362 00363 write_state <= '1' after 1 ns; 00364 00365 00366 fifo_sof <= '0' after 1 ns; 00367 fifo_eof <= '1' after 1 ns; 00368 fifo_rrem <= adr64 after 1 ns; 00369 fifo_data <= tlp_write_dw0 & tlp_write_dw1 after 1 ns; 00370 fifo_wr <= '1' after 1 ns; 00371 00372 write_cnt_en <= '1' after 1 ns; 00373 stp <= sw2 after 1 ns; 00374 00375 00376 when sw2 => 00377 fifo_sof <= '1' after 1 ns; 00378 if( adr64='1' ) then 00379 fifo_data <= tlp_write_dw2 & tlp_write_dw3 after 1 ns; 00380 else 00381 fifo_data <= tlp_write_dw3 & tlp_write_data( 63 downto 32 ) after 1 ns; 00382 end if; 00383 00384 stp <= sw3 after 1 ns; 00385 00386 when sw3 => 00387 if( adr64='1' ) then 00388 fifo_data <= tlp_write_data after 1 ns; 00389 else 00390 fifo_data( 31 downto 0 ) <= tlp_write_data( 63 downto 32 ) after 1 ns; 00391 fifo_data( 63 downto 32 ) <= tlp_write_data_z( 31 downto 0 ) after 1 ns; 00392 end if; 00393 00394 00395 fifo_wr <= '1' after 1 ns; 00396 if( write_cnt_eq='1' ) then 00397 stp <= sw5 after 1 ns; 00398 -- elsif( fifo_paf='1' ) then 00399 -- stp <= sw4 after 1 ns; 00400 end if; 00401 00402 -- when sw4 => 00403 -- write_cnt_en <= '0' after 1 ns; 00404 -- fifo_wr <= '0' after 1 ns; 00405 -- if( fifo_paf='0' ) then 00406 -- stp <= sw3 after 1 ns; 00407 -- end if; 00408 00409 when sw5 => 00410 if( adr64='1' ) then 00411 fifo_data <= tlp_write_data after 1 ns; 00412 else 00413 fifo_data( 31 downto 0 ) <= tlp_write_data( 63 downto 32 ) after 1 ns; 00414 fifo_data( 63 downto 32 ) <= tlp_write_data_z( 31 downto 0 ) after 1 ns; 00415 end if; 00416 00417 fifo_eof <= '0' after 1 ns; 00418 write_cnt_en <= '0' after 1 ns; 00419 if( write_cnt_pkg_eq='1' ) then 00420 stp <= sw6 after 1 ns; 00421 else 00422 stp <= s0 after 1 ns; 00423 end if; 00424 00425 when sw6 => 00426 fifo_wr <= '0' after 1 ns; 00427 tx_ext_fifo.complete_ok <= '1' after 1 ns; 00428 tx_ext_fifo.complete_error <= '0' after 1 ns; 00429 write_state <= '0' after 1 ns; 00430 if( tx_ext_fifo_back.req_wr='0' ) then 00431 stp <= s0 after 1 ns; 00432 end if; 00433 00434 00435 00436 00437 00438 end case; 00439 00440 00441 00442 00443 00444 if( rstpz='1' ) then 00445 stp <= s0 after 1 ns; 00446 wait_complete <= '0' after 1 ns; 00447 write_state <= '0' after 1 ns; 00448 end if; 00449 00450 end if; 00451 end process; 00452 00453 00454 tlp_dw0 <= "0" & rx_tx_engine.request_reg_rd & "0010100" & rx_tx_engine.request_tc & "0000" & rx_tx_engine.request_attr & "0000" & "0000000" & rx_tx_engine.request_reg_rd; 00455 tlp_dw1 <= completer_id & cpl_status & '0' & cpl_byte_count; 00456 tlp_dw2 <= rx_tx_engine.request_id & rx_tx_engine.request_tag & x"00"; 00457 00458 cpl_byte_count <= "0000" & "0000" & "0" & rx_tx_engine.request_reg_rd & "00"; 00459 00460 reg_data <= reg_access_back.data after 1 ns when rising_edge( clk ) and reg_access_back.data_we='1'; 00461 tlp_dw3( 7 downto 0 ) <= reg_data( 31 downto 24 ); 00462 tlp_dw3( 15 downto 8 ) <= reg_data( 23 downto 16 ); 00463 tlp_dw3( 23 downto 16 ) <= reg_data( 15 downto 8 ); 00464 tlp_dw3( 31 downto 24 ) <= reg_data( 7 downto 0 ); 00465 00466 max_read_size <= x"20"; -- 128 байт 00467 read_tag <= "000" & req_cnt( 4 downto 0 ); 00468 00469 adr64 <= tx_ext_fifo_back.pci_adr( 39 ) or 00470 tx_ext_fifo_back.pci_adr( 38 ) or 00471 tx_ext_fifo_back.pci_adr( 37 ) or 00472 tx_ext_fifo_back.pci_adr( 36 ) or 00473 tx_ext_fifo_back.pci_adr( 35 ) or 00474 tx_ext_fifo_back.pci_adr( 34 ) or 00475 tx_ext_fifo_back.pci_adr( 33 ) or 00476 tx_ext_fifo_back.pci_adr( 32 ); 00477 00478 tlp_read_dw0 <= "00" & adr64 & '0' & x"000" & "00000000" & max_read_size; 00479 tlp_read_dw1 <= completer_id & read_tag & x"FF"; 00480 tlp_read_dw2 <= x"000000" & tx_ext_fifo_back.pci_adr( 39 downto 32 ); 00481 tlp_read_dw3( 6 downto 0 ) <= "0000000"; 00482 tlp_read_dw3( 8 downto 7 ) <= req_cnt( 1 downto 0 ); 00483 tlp_read_dw3( 11 downto 9 ) <= req_cnt( 4 downto 2 ) when tx_ext_fifo_back.rd_size='1' 00484 else tx_ext_fifo_back.pci_adr( 11 downto 9 ); 00485 00486 tlp_read_dw3( 31 downto 12 ) <= tx_ext_fifo_back.pci_adr( 31 downto 12 ); 00487 00488 00489 --tlp_read_dw0 <= x"0000" & "00000000" & max_read_size; 00490 --tlp_read_dw1 <= completer_id & read_tag & x"FF"; 00491 -- 00492 --tlp_read_dw2( 6 downto 0 ) <= "0000000"; 00493 --tlp_read_dw2( 8 downto 7 ) <= req_cnt( 1 downto 0 ); 00494 --tlp_read_dw2( 11 downto 9 ) <= req_cnt( 4 downto 2 ) when tx_ext_fifo_back.rd_size='1' 00495 -- else tx_ext_fifo_back.pci_adr( 11 downto 9 ); 00496 -- 00497 --tlp_read_dw2( 31 downto 12 ) <= tx_ext_fifo_back.pci_adr( 31 downto 12 ); 00498 -- 00499 --tlp_read_dw3 <= (others=>'0'); 00500 00501 00502 00503 pr_req_cnt: process( clk ) begin 00504 if( rising_edge( clk ) ) then 00505 if( stp=s0 and wait_complete='0' ) then 00506 req_cnt <= (others=>'0') after 1 ns; 00507 elsif( stp=sr3 ) then 00508 req_cnt <= req_cnt + 1 after 1 ns; 00509 end if; 00510 end if; 00511 end process; 00512 00513 00514 00515 rstpz1 <= rstpz after 1 ns when rising_edge( clk ); 00516 timeout_st0 <= ( not rstpz ) and (rstpz1 or timeout_cnt_en ) after 1 ns when rising_edge( clk ); 00517 00518 xtcnt: srlc32e port map( q31=>timeout_cnt_en, clk=>clk, d =>timeout_st0, a =>"11111", ce=>'1' ); 00519 00520 pr_timeout_cnt: process( clk ) begin 00521 if( rising_edge( clk ) ) then 00522 if( wait_complete='0' ) then 00523 timeout_cnt <= (others=>'0') after 1 ns; 00524 elsif( timeout_cnt_en='1' ) then 00525 timeout_cnt <= timeout_cnt + 1 after 1 ns; 00526 end if; 00527 end if; 00528 end process; 00529 00530 timeout_error <= timeout_cnt(10); 00531 00532 pr_complete_cnt: process( clk ) begin 00533 if( rising_edge( clk ) ) then 00534 if( wait_complete='0' ) then 00535 if( tx_ext_fifo_back.rd_size='0' ) then 00536 complete_cnt <= "0111000000" after 1 ns; -- 513-64 -- ожидается 512 байт 00537 else 00538 complete_cnt <= "0000000000" after 1 ns; -- ожидается 4096 байт (512 слов по 8 байт) 00539 end if; 00540 elsif( rx_tx_engine.complete_we='1' ) then 00541 complete_cnt <= complete_cnt + 1 after 1 ns; 00542 end if; 00543 end if; 00544 end process; 00545 00546 req_complete <= complete_cnt(9); 00547 00548 write_size <= trn_tx_back.cfg_dcommand(5); 00549 00550 pr_write_cnt: process( clk ) begin 00551 if( rising_edge( clk ) ) then 00552 if( stp=s0 ) then 00553 write_cnt <= '0' & not write_size & "000" & adr64 after 1 ns; 00554 elsif( write_cnt_en='1' ) then 00555 write_cnt <= write_cnt + 1 after 1 ns; 00556 end if; 00557 end if; 00558 end process; 00559 00560 write_cnt_eq <= write_cnt(5); 00561 00562 write_cnt_pkg_add <= write_size & not write_size; 00563 00564 pr_write_cnt_pkg: process( clk ) begin 00565 if( rising_edge( clk ) ) then 00566 if( stp=s0 and write_state='0' ) then 00567 write_cnt_pkg <= "00000" after 1 ns; 00568 elsif( stp=sw5 ) then 00569 write_cnt_pkg <= write_cnt_pkg + write_cnt_pkg_add after 1 ns; 00570 end if; 00571 end if; 00572 end process; 00573 00574 write_cnt_pkg_eq <= write_cnt_pkg(4) and write_cnt_pkg(3) and write_cnt_pkg(2) and write_cnt_pkg(1) and (write_cnt_pkg(0) or write_size); 00575 00576 00577 tlp_write_dw0 <= "01" & adr64 & '0' & x"000" & "00000000" & "0" & write_size & not write_size & "00000"; 00578 tlp_write_dw1 <= tlp_read_dw1; 00579 tlp_write_dw2 <= tlp_read_dw2; --x"000000" & tx_ext_fifo_back.pci_adr( 39 downto 32 ); 00580 tlp_write_dw3( 6 downto 0 ) <= "0000000"; 00581 tlp_write_dw3( 11 downto 7 ) <= write_cnt_pkg( 4 downto 0 ); 00582 tlp_write_dw3( 31 downto 12 ) <= tx_ext_fifo_back.pci_adr( 31 downto 12 ); 00583 00584 00585 --tlp_write_data <= x"00000000" & x"0000" & "0000000000" & write_cnt; 00586 gen_repack: for ii in 0 to 7 generate 00587 tlp_write_data( ii*8+7 downto ii*8 ) <= tx_ext_fifo_back.data( (7-ii)*8+7 downto (7-ii)*8 ); 00588 end generate; 00589 00590 tlp_write_data_z <= tlp_write_data( 31 downto 0 ) after 1 ns when rising_edge( clk ); 00591 00592 pr_adr_cnt: process( clk ) begin 00593 if( rising_edge( clk ) ) then 00594 if( write_cnt_en='0' ) then 00595 adr_cnt <= (others=>'0') after 1 ns; 00596 else 00597 adr_cnt <= adr_cnt + 1 after 1 ns; 00598 end if; 00599 end if; 00600 end process; 00601 00602 tx_ext_fifo.adr( 3 downto 0 ) <= adr_cnt( 3 downto 0 ); 00603 tx_ext_fifo.adr( 4 ) <= adr_cnt(4) or write_cnt_pkg(0); 00604 tx_ext_fifo.adr( 8 downto 5 ) <= write_cnt_pkg( 4 downto 1 ); 00605 00606 00607 trn_tx.fc_sel <= "000"; 00608 trn_tx.tx_cfg_gnt <= '1'; 00609 --trn_tx.s_axis_tx_tvalid <= '0'; 00610 -- 00611 --trn_tx.s_axis_tx_tstrb <= (others=>'0'); 00612 --trn_tx.s_axis_tx_tuser <= (others=>'0'); 00613 --trn_tx.s_axis_tx_tlast <= '0'; 00614 00615 end core64_tx_engine_m2;
1.7.4