DS_DMA
Components | Signals | Types | Component Instantiations | Functions | Processes
core64_tx_engine_m2 Architecture Reference
Граф наследования:core64_tx_engine_m2:
ctrl_fifo64x67fw ctrl_fifo64x67fw_a core64_tx_engine_m2 core64_tx_engine_m2_pkg pcie_core64_m4 pcie_core64_m4 pcie_core64_m4_pkg pcie_core64_m5 pcie_core64_m5 pcie_core64_m5_pkg

Полный список членов класса



Functions

std_logic_vector   set_data ( data_in: in std_logic_vector( 63 downto 0 ) )

Processes

pr_state  ( clk )
pr_req_cnt  ( clk )
pr_timeout_cnt  ( clk )
pr_complete_cnt  ( clk )
pr_write_cnt  ( clk )
pr_write_cnt_pkg  ( clk )
pr_adr_cnt  ( clk )

Components

ctrl_fifo64x67fw  <Entity ctrl_fifo64x67fw>

Types

stp_type  ( s0 , s1 , s2 , s3 , s4 , sr1 , sr2 , sr3 , sr4 , sr5 , sw1 , sw01 , sw2 , sw3 , sw5 , sw6 )

Signals

rstpz  std_logic
stp  stp_type
fifo_din  std_logic_vector ( 66 downto 0 )
fifo_wr  std_logic
fifo_rd  std_logic
fifo_dout  std_logic_vector ( 66 downto 0 )
fifo_full  std_logic
fifo_empty  std_logic
fifo_valid  std_logic
fifo_paf  std_logic
fifo_pae  std_logic
fifo_sof  std_logic
fifo_eof  std_logic
fifo_rrem  std_logic
fifo_data  std_logic_vector ( 63 downto 0 )
reg_data  std_logic_vector ( 31 downto 0 )
tlp_dw0  std_logic_vector ( 31 downto 0 )
tlp_dw1  std_logic_vector ( 31 downto 0 )
tlp_dw2  std_logic_vector ( 31 downto 0 )
tlp_dw3  std_logic_vector ( 31 downto 0 )
cpl_status  std_logic_vector ( 2 downto 0 ) := " 000 "
cpl_byte_count  std_logic_vector ( 11 downto 0 ) := x " 000 "
tlp_read_dw0  std_logic_vector ( 31 downto 0 )
tlp_read_dw1  std_logic_vector ( 31 downto 0 )
tlp_read_dw2  std_logic_vector ( 31 downto 0 )
tlp_read_dw3  std_logic_vector ( 31 downto 0 )
max_read_size  std_logic_vector ( 7 downto 0 )
read_tag  std_logic_vector ( 7 downto 0 )
req_cnt  std_logic_vector ( 5 downto 0 )
 счётчик запросов
req_complete  std_logic
 1 - получены все ответы
wait_complete  std_logic
complete_cnt  std_logic_vector ( 9 downto 0 )
 счётчик принятых слов
timeout_cnt  std_logic_vector ( 10 downto 0 )
 ожидание ответа
timeout_cnt_en  std_logic
timeout_error  std_logic
timeout_st0  std_logic
rstpz1  std_logic
write_cnt_en  std_logic
write_cnt  std_logic_vector ( 5 downto 0 )
 счётчик слов в пакете
write_cnt_pkg  std_logic_vector ( 4 downto 0 )
 счётчик пакетов
write_cnt_eq  std_logic
write_cnt_pkg_eq  std_logic
write_state  std_logic
write_size  std_logic
 1 - пакет 256 байт, 0 - пакет 128 байт
write_cnt_pkg_add  std_logic_vector ( 1 downto 0 )
tlp_write_dw0  std_logic_vector ( 31 downto 0 )
tlp_write_dw1  std_logic_vector ( 31 downto 0 )
tlp_write_dw2  std_logic_vector ( 31 downto 0 )
tlp_write_dw3  std_logic_vector ( 31 downto 0 )
tlp_write_data  std_logic_vector ( 63 downto 0 )
tlp_write_data_z  std_logic_vector ( 31 downto 0 )
adr_cnt  std_logic_vector ( 5 downto 0 )
adr64  std_logic
axis_tx_tstrb_h  std_logic
allow_wr  std_logic
allow_cpl  std_logic
tbuf_av  std_logic_vector ( 5 downto 0 )

Component Instantiations

fifo0_reg  ctrl_fifo64x67fw <Entity ctrl_fifo64x67fw>
xtcnt  srlc32e

Подробное описание

См. определение в файле core64_tx_engine_m2.vhd строка 88


Объявления и описания членов класса находятся в файле: