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DS_DMA
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00001 --------------------------------------------------------------------------------------------------- 00002 -- 00003 -- Title : ctrl_ram16_v1 00004 -- Author : Dmitry Smekhov 00005 -- Company : Instrumental System 00006 -- E-mail : dsmv@insys.ru 00007 -- 00008 -- Version : 1.0 00009 -- 00010 --------------------------------------------------------------------------------------------------- 00011 -- 00012 -- Description : Теневое ОЗУ для командных регистров и констант 00013 -- 00014 --------------------------------------------------------------------------------------------------- 00015 00016 library ieee; 00017 use ieee.std_logic_1164.all; 00018 00019 library work; 00020 use work.host_pkg.all; 00021 00022 package ctrl_ram16_v1_pkg is 00023 00024 component ctrl_ram16_v1 is 00025 generic ( 00026 rom : in bh_rom -- значения констант 00027 ); 00028 port( 00029 clk : in std_logic; -- Тактовая частота 00030 00031 adr : in std_logic_vector( 4 downto 0 ); -- адрес 00032 data_in : in std_logic_vector( 15 downto 0 ); -- вход данных 00033 data_out : out std_logic_vector( 15 downto 0 ); -- выход данных 00034 00035 data_we : in std_logic -- 1 - запись данных 00036 00037 ); 00038 end component; 00039 00040 end package ctrl_ram16_v1_pkg; 00041 00042 00043 00044 00045 library ieee; 00046 use ieee.std_logic_1164.all; 00047 00048 library unisim; 00049 use unisim.vcomponents.all; 00050 00051 library work; 00052 use work.host_pkg.all; 00053 00054 00055 00056 entity ctrl_ram16_v1 is 00057 generic ( 00058 rom : in bh_rom -- значения констант 00059 ); 00060 port( 00061 clk : in std_logic; -- Тактовая частота 00062 00063 adr : in std_logic_vector( 4 downto 0 ); -- адрес 00064 data_in : in std_logic_vector( 15 downto 0 ); -- вход данных 00065 data_out : out std_logic_vector( 15 downto 0 ); -- выход данных 00066 00067 data_we : in std_logic -- 1 - запись данных 00068 00069 ); 00070 end ctrl_ram16_v1; 00071 00072 00073 architecture ctrl_ram16_v1 of ctrl_ram16_v1 is 00074 00075 function conv_rom( rom: in bh_rom; mode: integer ) return bit_vector is 00076 variable ret: bit_vector( 15 downto 0 ); 00077 begin 00078 for i in 0 to 7 loop 00079 ret( i ):=to_bit( rom( i )( mode ), '0' ); 00080 end loop; 00081 for i in 8 to 15 loop 00082 ret( i ):='0'; 00083 end loop; 00084 return ret; 00085 end conv_rom; 00086 00087 function conv_string( rom: in bh_rom; mode: integer ) return string is 00088 variable str: string( 4 downto 1 ); 00089 00090 variable d : std_logic_vector( 15 downto 0 ); 00091 variable c : std_logic_vector( 3 downto 0 ); 00092 variable k : integer; 00093 begin 00094 00095 00096 00097 for i in 0 to 7 loop 00098 d(i):=rom( i )( mode ); 00099 end loop; 00100 for i in 8 to 15 loop 00101 d(i):='0'; 00102 end loop; 00103 00104 for j in 0 to 3 loop 00105 c:=d( j*4+3 downto j*4 ); 00106 k:=j+1; 00107 case c is 00108 when x"0" => str(k) := '0'; 00109 when x"1" => str(k) := '1'; 00110 when x"2" => str(k) := '2'; 00111 when x"3" => str(k) := '3'; 00112 when x"4" => str(k) := '4'; 00113 when x"5" => str(k) := '5'; 00114 when x"6" => str(k) := '6'; 00115 when x"7" => str(k) := '7'; 00116 when x"8" => str(k) := '8'; 00117 when x"9" => str(k) := '9'; 00118 when x"A" => str(k) := 'A'; 00119 when x"B" => str(k) := 'B'; 00120 when x"C" => str(k) := 'C'; 00121 when x"D" => str(k) := 'D'; 00122 when x"E" => str(k) := 'E'; 00123 when x"F" => str(k) := 'F'; 00124 when others => null; 00125 end case; 00126 end loop; 00127 00128 return str; 00129 end conv_string; 00130 00131 00132 constant rom_init_00 : bit_vector( 15 downto 0 ):= conv_rom( rom, 0 ); 00133 constant rom_init_01 : bit_vector( 15 downto 0 ):= conv_rom( rom, 1 ); 00134 constant rom_init_02 : bit_vector( 15 downto 0 ):= conv_rom( rom, 2 ); 00135 constant rom_init_03 : bit_vector( 15 downto 0 ):= conv_rom( rom, 3 ); 00136 constant rom_init_04 : bit_vector( 15 downto 0 ):= conv_rom( rom, 4 ); 00137 constant rom_init_05 : bit_vector( 15 downto 0 ):= conv_rom( rom, 5 ); 00138 constant rom_init_06 : bit_vector( 15 downto 0 ):= conv_rom( rom, 6 ); 00139 constant rom_init_07 : bit_vector( 15 downto 0 ):= conv_rom( rom, 7 ); 00140 constant rom_init_08 : bit_vector( 15 downto 0 ):= conv_rom( rom, 8 ); 00141 constant rom_init_09 : bit_vector( 15 downto 0 ):= conv_rom( rom, 9 ); 00142 constant rom_init_0A : bit_vector( 15 downto 0 ):= conv_rom( rom, 10 ); 00143 constant rom_init_0B : bit_vector( 15 downto 0 ):= conv_rom( rom, 11 ); 00144 constant rom_init_0C : bit_vector( 15 downto 0 ):= conv_rom( rom, 12 ); 00145 constant rom_init_0D : bit_vector( 15 downto 0 ):= conv_rom( rom, 13 ); 00146 constant rom_init_0E : bit_vector( 15 downto 0 ):= conv_rom( rom, 14 ); 00147 constant rom_init_0F : bit_vector( 15 downto 0 ):= conv_rom( rom, 15 ); 00148 00149 00150 00151 constant str_init_00 : string:= conv_string( rom, 0 ); 00152 constant str_init_01 : string:= conv_string( rom, 1 ); 00153 constant str_init_02 : string:= conv_string( rom, 2 ); 00154 constant str_init_03 : string:= conv_string( rom, 3 ); 00155 constant str_init_04 : string:= conv_string( rom, 4 ); 00156 constant str_init_05 : string:= conv_string( rom, 5 ); 00157 constant str_init_06 : string:= conv_string( rom, 6 ); 00158 constant str_init_07 : string:= conv_string( rom, 7 ); 00159 constant str_init_08 : string:= conv_string( rom, 8 ); 00160 constant str_init_09 : string:= conv_string( rom, 9 ); 00161 constant str_init_0A : string:= conv_string( rom, 10 ); 00162 constant str_init_0B : string:= conv_string( rom, 11 ); 00163 constant str_init_0C : string:= conv_string( rom, 12 ); 00164 constant str_init_0D : string:= conv_string( rom, 13 ); 00165 constant str_init_0E : string:= conv_string( rom, 14 ); 00166 constant str_init_0F : string:= conv_string( rom, 15 ); 00167 00168 00169 --attribute rom_style : string; 00170 --attribute rom_style of xram : label is "block"; 00171 00172 --attribute init : string; 00173 -- 00174 --attribute init of xram0 : label is str_init_00; 00175 --attribute init of xram1 : label is str_init_01; 00176 --attribute init of xram2 : label is str_init_02; 00177 --attribute init of xram3 : label is str_init_03; 00178 --attribute init of xram4 : label is str_init_04; 00179 --attribute init of xram5 : label is str_init_05; 00180 --attribute init of xram6 : label is str_init_06; 00181 --attribute init of xram7 : label is str_init_07; 00182 --attribute init of xram8 : label is str_init_08; 00183 --attribute init of xram9 : label is str_init_09; 00184 --attribute init of xram10 : label is str_init_0A; 00185 --attribute init of xram11 : label is str_init_0B; 00186 --attribute init of xram12 : label is str_init_0C; 00187 --attribute init of xram13 : label is str_init_0D; 00188 --attribute init of xram14 : label is str_init_0E; 00189 --attribute init of xram15 : label is str_init_0F; 00190 -- 00191 00192 00193 signal wr : std_logic; -- 1 - запись в память 00194 begin 00195 00196 wr <= '1' when data_we='1' and adr(4)='0' and adr(3)='1' else '0'; 00197 00198 00199 xram0: ram16x1d 00200 generic map( 00201 init => rom_init_00 00202 ) 00203 port map( 00204 we => wr, 00205 d => data_in( 0 ), 00206 wclk => clk, 00207 a0 => adr( 0 ), 00208 a1 => adr( 1 ), 00209 a2 => adr( 2 ), 00210 a3 => adr( 3 ), 00211 spo => data_out( 0 ), 00212 dpra0 => adr( 0 ), 00213 dpra1 => adr( 1 ), 00214 dpra2 => adr( 2 ), 00215 dpra3 => adr( 3 ) 00216 ); 00217 00218 xram1: ram16x1d 00219 generic map( 00220 init => rom_init_01 00221 ) 00222 port map( 00223 we => wr, 00224 d => data_in( 1 ), 00225 wclk => clk, 00226 a0 => adr( 0 ), 00227 a1 => adr( 1 ), 00228 a2 => adr( 2 ), 00229 a3 => adr( 3 ), 00230 spo => data_out( 1 ), 00231 dpra0 => adr( 0 ), 00232 dpra1 => adr( 1 ), 00233 dpra2 => adr( 2 ), 00234 dpra3 => adr( 3 ) 00235 ); 00236 00237 xram2: ram16x1d 00238 generic map( 00239 init => rom_init_02 00240 ) 00241 port map( 00242 we => wr, 00243 d => data_in( 2 ), 00244 wclk => clk, 00245 a0 => adr( 0 ), 00246 a1 => adr( 1 ), 00247 a2 => adr( 2 ), 00248 a3 => adr( 3 ), 00249 spo => data_out( 2 ), 00250 dpra0 => adr( 0 ), 00251 dpra1 => adr( 1 ), 00252 dpra2 => adr( 2 ), 00253 dpra3 => adr( 3 ) 00254 ); 00255 00256 xram3: ram16x1d 00257 generic map( 00258 init => rom_init_03 00259 ) 00260 port map( 00261 we => wr, 00262 d => data_in( 3 ), 00263 wclk => clk, 00264 a0 => adr( 0 ), 00265 a1 => adr( 1 ), 00266 a2 => adr( 2 ), 00267 a3 => adr( 3 ), 00268 spo => data_out( 3 ), 00269 dpra0 => adr( 0 ), 00270 dpra1 => adr( 1 ), 00271 dpra2 => adr( 2 ), 00272 dpra3 => adr( 3 ) 00273 ); 00274 00275 xram4: ram16x1d 00276 generic map( 00277 init => rom_init_04 00278 ) 00279 port map( 00280 we => wr, 00281 d => data_in( 4 ), 00282 wclk => clk, 00283 a0 => adr( 0 ), 00284 a1 => adr( 1 ), 00285 a2 => adr( 2 ), 00286 a3 => adr( 3 ), 00287 spo => data_out( 4 ), 00288 dpra0 => adr( 0 ), 00289 dpra1 => adr( 1 ), 00290 dpra2 => adr( 2 ), 00291 dpra3 => adr( 3 ) 00292 ); 00293 00294 xram5: ram16x1d 00295 generic map( 00296 init => rom_init_05 00297 ) 00298 port map( 00299 we => wr, 00300 d => data_in( 5 ), 00301 wclk => clk, 00302 a0 => adr( 0 ), 00303 a1 => adr( 1 ), 00304 a2 => adr( 2 ), 00305 a3 => adr( 3 ), 00306 spo => data_out( 5 ), 00307 dpra0 => adr( 0 ), 00308 dpra1 => adr( 1 ), 00309 dpra2 => adr( 2 ), 00310 dpra3 => adr( 3 ) 00311 ); 00312 00313 xram6: ram16x1d 00314 generic map( 00315 init => rom_init_06 00316 ) 00317 port map( 00318 we => wr, 00319 d => data_in( 6 ), 00320 wclk => clk, 00321 a0 => adr( 0 ), 00322 a1 => adr( 1 ), 00323 a2 => adr( 2 ), 00324 a3 => adr( 3 ), 00325 spo => data_out( 6 ), 00326 dpra0 => adr( 0 ), 00327 dpra1 => adr( 1 ), 00328 dpra2 => adr( 2 ), 00329 dpra3 => adr( 3 ) 00330 ); 00331 00332 xram7: ram16x1d 00333 generic map( 00334 init => rom_init_07 00335 ) 00336 port map( 00337 we => wr, 00338 d => data_in( 7 ), 00339 wclk => clk, 00340 a0 => adr( 0 ), 00341 a1 => adr( 1 ), 00342 a2 => adr( 2 ), 00343 a3 => adr( 3 ), 00344 spo => data_out( 7 ), 00345 dpra0 => adr( 0 ), 00346 dpra1 => adr( 1 ), 00347 dpra2 => adr( 2 ), 00348 dpra3 => adr( 3 ) 00349 ); 00350 00351 xram8: ram16x1d 00352 generic map( 00353 init => rom_init_08 00354 ) 00355 port map( 00356 we => wr, 00357 d => data_in( 8 ), 00358 wclk => clk, 00359 a0 => adr( 0 ), 00360 a1 => adr( 1 ), 00361 a2 => adr( 2 ), 00362 a3 => adr( 3 ), 00363 spo => data_out( 8 ), 00364 dpra0 => adr( 0 ), 00365 dpra1 => adr( 1 ), 00366 dpra2 => adr( 2 ), 00367 dpra3 => adr( 3 ) 00368 ); 00369 00370 xram9: ram16x1d 00371 generic map( 00372 init => rom_init_09 00373 ) 00374 port map( 00375 we => wr, 00376 d => data_in( 9 ), 00377 wclk => clk, 00378 a0 => adr( 0 ), 00379 a1 => adr( 1 ), 00380 a2 => adr( 2 ), 00381 a3 => adr( 3 ), 00382 spo => data_out( 9 ), 00383 dpra0 => adr( 0 ), 00384 dpra1 => adr( 1 ), 00385 dpra2 => adr( 2 ), 00386 dpra3 => adr( 3 ) 00387 ); 00388 00389 xram10: ram16x1d 00390 generic map( 00391 init => rom_init_0A 00392 ) 00393 port map( 00394 we => wr, 00395 d => data_in( 10 ), 00396 wclk => clk, 00397 a0 => adr( 0 ), 00398 a1 => adr( 1 ), 00399 a2 => adr( 2 ), 00400 a3 => adr( 3 ), 00401 spo => data_out( 10 ), 00402 dpra0 => adr( 0 ), 00403 dpra1 => adr( 1 ), 00404 dpra2 => adr( 2 ), 00405 dpra3 => adr( 3 ) 00406 ); 00407 00408 xram11: ram16x1d 00409 generic map( 00410 init => rom_init_0B 00411 ) 00412 port map( 00413 we => wr, 00414 d => data_in( 11 ), 00415 wclk => clk, 00416 a0 => adr( 0 ), 00417 a1 => adr( 1 ), 00418 a2 => adr( 2 ), 00419 a3 => adr( 3 ), 00420 spo => data_out( 11 ), 00421 dpra0 => adr( 0 ), 00422 dpra1 => adr( 1 ), 00423 dpra2 => adr( 2 ), 00424 dpra3 => adr( 3 ) 00425 ); 00426 00427 xram12: ram16x1d 00428 generic map( 00429 init => rom_init_0C 00430 ) 00431 port map( 00432 we => wr, 00433 d => data_in( 12 ), 00434 wclk => clk, 00435 a0 => adr( 0 ), 00436 a1 => adr( 1 ), 00437 a2 => adr( 2 ), 00438 a3 => adr( 3 ), 00439 spo => data_out( 12 ), 00440 dpra0 => adr( 0 ), 00441 dpra1 => adr( 1 ), 00442 dpra2 => adr( 2 ), 00443 dpra3 => adr( 3 ) 00444 ); 00445 00446 xram13: ram16x1d 00447 generic map( 00448 init => rom_init_0D 00449 ) 00450 port map( 00451 we => wr, 00452 d => data_in( 13 ), 00453 wclk => clk, 00454 a0 => adr( 0 ), 00455 a1 => adr( 1 ), 00456 a2 => adr( 2 ), 00457 a3 => adr( 3 ), 00458 spo => data_out( 13 ), 00459 dpra0 => adr( 0 ), 00460 dpra1 => adr( 1 ), 00461 dpra2 => adr( 2 ), 00462 dpra3 => adr( 3 ) 00463 ); 00464 00465 xram14: ram16x1d 00466 generic map( 00467 init => rom_init_0E 00468 ) 00469 port map( 00470 we => wr, 00471 d => data_in( 14 ), 00472 wclk => clk, 00473 a0 => adr( 0 ), 00474 a1 => adr( 1 ), 00475 a2 => adr( 2 ), 00476 a3 => adr( 3 ), 00477 spo => data_out( 14 ), 00478 dpra0 => adr( 0 ), 00479 dpra1 => adr( 1 ), 00480 dpra2 => adr( 2 ), 00481 dpra3 => adr( 3 ) 00482 ); 00483 00484 xram15: ram16x1d 00485 generic map( 00486 init => rom_init_0F 00487 ) 00488 port map( 00489 we => wr, 00490 d => data_in( 15 ), 00491 wclk => clk, 00492 a0 => adr( 0 ), 00493 a1 => adr( 1 ), 00494 a2 => adr( 2 ), 00495 a3 => adr( 3 ), 00496 spo => data_out( 15 ), 00497 dpra0 => adr( 0 ), 00498 dpra1 => adr( 1 ), 00499 dpra2 => adr( 2 ), 00500 dpra3 => adr( 3 ) 00501 ); 00502 00503 00504 end ctrl_ram16_v1;
1.7.4