|
DS_DMA
|
Architectures | |
| ctrl_ram16_v1 | Architecture |
Libraries | |
| ieee | |
| unisim | |
| work | |
Packages | |
| std_logic_1164 | |
| vcomponents | |
| host_pkg | Package <host_pkg> |
Generics | |
| rom | in bh_rom |
Ports | |
| clk | in std_logic |
| adr | in std_logic_vector ( 4 downto 0 ) |
| data_in | in std_logic_vector ( 15 downto 0 ) |
| data_out | out std_logic_vector ( 15 downto 0 ) |
| data_we | in std_logic |
См. определение в файле ctrl_ram16_v1.vhd строка 56
1.7.4