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DS_DMA
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00001 ------------------------------------------------------------------------------- 00002 -- ____ ____ 00003 -- / /\/ / 00004 -- /___/ \ / Vendor: Xilinx 00005 -- \ \ \/ Version : 1.7 00006 -- \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard 00007 -- / / Filename : gtpa1_dual_wrapper.vhd 00008 -- /___/ /\ Timestamp : 00009 -- \ \ / \ 00010 -- \___\/\___\ 00011 -- 00012 -- 00013 -- Module GTPA1_DUAL_WRAPPER (a GTP Wrapper) 00014 -- Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard 00015 -- 00016 -- 00017 -- (c) Copyright 2009 Xilinx, Inc. All rights reserved. 00018 -- 00019 -- This file contains confidential and proprietary information 00020 -- of Xilinx, Inc. and is protected under U.S. and 00021 -- international copyright and other intellectual property 00022 -- laws. 00023 -- 00024 -- DISCLAIMER 00025 -- This disclaimer is not a license and does not grant any 00026 -- rights to the materials distributed herewith. Except as 00027 -- otherwise provided in a valid license issued to you by 00028 -- Xilinx, and to the maximum extent permitted by applicable 00029 -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 00030 -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 00031 -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 00032 -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 00033 -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 00034 -- (2) Xilinx shall not be liable (whether in contract or tort, 00035 -- including negligence, or under any other theory of 00036 -- liability) for any loss or damage of any kind or nature 00037 -- related to, arising under or in connection with these 00038 -- materials, including for any direct, or any indirect, 00039 -- special, incidental, or consequential loss or damage 00040 -- (including loss of data, profits, goodwill, or any type of 00041 -- loss or damage suffered as a result of any action brought 00042 -- by a third party) even if such damage or loss was 00043 -- reasonably foreseeable or Xilinx had been advised of the 00044 -- possibility of the same. 00045 -- 00046 -- CRITICAL APPLICATIONS 00047 -- Xilinx products are not designed or intended to be fail- 00048 -- safe, or for use in any application requiring fail-safe 00049 -- performance, such as life-support or safety devices or 00050 -- systems, Class III medical devices, nuclear facilities, 00051 -- applications related to the deployment of airbags, or any 00052 -- other applications that could lead to death, personal 00053 -- injury, or severe property or environmental damage 00054 -- (individually and collectively, "Critical 00055 -- Applications"). Customer assumes the sole risk and 00056 -- liability of any use of Xilinx products in Critical 00057 -- Applications, subject only to applicable laws and 00058 -- regulations governing limitations on product liability. 00059 -- 00060 -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 00061 -- PART OF THIS FILE AT ALL TIMES. 00062 00063 00064 library ieee; 00065 use ieee.std_logic_1164.all; 00066 use ieee.numeric_std.all; 00067 library UNISIM; 00068 use UNISIM.VCOMPONENTS.ALL; 00069 00070 00071 --***************************** Entity Declaration **************************** 00072 00073 entity GTPA1_DUAL_WRAPPER is 00074 generic 00075 ( 00076 -- Simulation attributes 00077 WRAPPER_SIM_GTPRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset 00078 WRAPPER_CLK25_DIVIDER_0 : integer := 4; 00079 WRAPPER_CLK25_DIVIDER_1 : integer := 4; 00080 WRAPPER_PLL_DIVSEL_FB_0 : integer := 5; 00081 WRAPPER_PLL_DIVSEL_FB_1 : integer := 5; 00082 WRAPPER_PLL_DIVSEL_REF_0 : integer := 2; 00083 WRAPPER_PLL_DIVSEL_REF_1 : integer := 2; 00084 WRAPPER_SIMULATION : integer := 0 -- Set to 1 for simulation 00085 ); 00086 port 00087 ( 00088 00089 --_________________________________________________________________________ 00090 --_________________________________________________________________________ 00091 --TILE0 (X0_Y0) 00092 00093 ------------------------ Loopback and Powerdown Ports ---------------------- 00094 TILE0_RXPOWERDOWN0_IN : in std_logic_vector(1 downto 0); 00095 TILE0_RXPOWERDOWN1_IN : in std_logic_vector(1 downto 0); 00096 TILE0_TXPOWERDOWN0_IN : in std_logic_vector(1 downto 0); 00097 TILE0_TXPOWERDOWN1_IN : in std_logic_vector(1 downto 0); 00098 --------------------------------- PLL Ports -------------------------------- 00099 TILE0_CLK00_IN : in std_logic; 00100 TILE0_CLK01_IN : in std_logic; 00101 TILE0_GTPRESET0_IN : in std_logic; 00102 TILE0_GTPRESET1_IN : in std_logic; 00103 TILE0_PLLLKDET0_OUT : out std_logic; 00104 TILE0_PLLLKDET1_OUT : out std_logic; 00105 TILE0_RESETDONE0_OUT : out std_logic; 00106 TILE0_RESETDONE1_OUT : out std_logic; 00107 ----------------------- Receive Ports - 8b10b Decoder ---------------------- 00108 TILE0_RXCHARISK0_OUT : out std_logic_vector(1 downto 0); 00109 TILE0_RXCHARISK1_OUT : out std_logic_vector(1 downto 0); 00110 TILE0_RXDISPERR0_OUT : out std_logic_vector(1 downto 0); 00111 TILE0_RXDISPERR1_OUT : out std_logic_vector(1 downto 0); 00112 TILE0_RXNOTINTABLE0_OUT : out std_logic_vector(1 downto 0); 00113 TILE0_RXNOTINTABLE1_OUT : out std_logic_vector(1 downto 0); 00114 ---------------------- Receive Ports - Clock Correction -------------------- 00115 TILE0_RXCLKCORCNT0_OUT : out std_logic_vector(2 downto 0); 00116 TILE0_RXCLKCORCNT1_OUT : out std_logic_vector(2 downto 0); 00117 --------------- Receive Ports - Comma Detection and Alignment -------------- 00118 TILE0_RXENMCOMMAALIGN0_IN : in std_logic; 00119 TILE0_RXENMCOMMAALIGN1_IN : in std_logic; 00120 TILE0_RXENPCOMMAALIGN0_IN : in std_logic; 00121 TILE0_RXENPCOMMAALIGN1_IN : in std_logic; 00122 ------------------- Receive Ports - RX Data Path interface ----------------- 00123 TILE0_RXDATA0_OUT : out std_logic_vector(15 downto 0); 00124 TILE0_RXDATA1_OUT : out std_logic_vector(15 downto 0); 00125 TILE0_RXRESET0_IN : in std_logic; 00126 TILE0_RXRESET1_IN : in std_logic; 00127 TILE0_RXUSRCLK0_IN : in std_logic; 00128 TILE0_RXUSRCLK1_IN : in std_logic; 00129 TILE0_RXUSRCLK20_IN : in std_logic; 00130 TILE0_RXUSRCLK21_IN : in std_logic; 00131 ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ 00132 TILE0_GATERXELECIDLE0_IN : in std_logic; 00133 TILE0_GATERXELECIDLE1_IN : in std_logic; 00134 TILE0_IGNORESIGDET0_IN : in std_logic; 00135 TILE0_IGNORESIGDET1_IN : in std_logic; 00136 TILE0_RXELECIDLE0_OUT : out std_logic; 00137 TILE0_RXELECIDLE1_OUT : out std_logic; 00138 TILE0_RXN0_IN : in std_logic; 00139 TILE0_RXN1_IN : in std_logic; 00140 TILE0_RXP0_IN : in std_logic; 00141 TILE0_RXP1_IN : in std_logic; 00142 ----------- Receive Ports - RX Elastic Buffer and Phase Alignment ---------- 00143 TILE0_RXSTATUS0_OUT : out std_logic_vector(2 downto 0); 00144 TILE0_RXSTATUS1_OUT : out std_logic_vector(2 downto 0); 00145 -------------- Receive Ports - RX Pipe Control for PCI Express ------------- 00146 TILE0_PHYSTATUS0_OUT : out std_logic; 00147 TILE0_PHYSTATUS1_OUT : out std_logic; 00148 TILE0_RXVALID0_OUT : out std_logic; 00149 TILE0_RXVALID1_OUT : out std_logic; 00150 -------------------- Receive Ports - RX Polarity Control ------------------- 00151 TILE0_RXPOLARITY0_IN : in std_logic; 00152 TILE0_RXPOLARITY1_IN : in std_logic; 00153 ---------------------------- TX/RX Datapath Ports -------------------------- 00154 TILE0_GTPCLKOUT0_OUT : out std_logic_vector(1 downto 0); 00155 TILE0_GTPCLKOUT1_OUT : out std_logic_vector(1 downto 0); 00156 ------------------- Transmit Ports - 8b10b Encoder Control ----------------- 00157 TILE0_TXCHARDISPMODE0_IN : in std_logic_vector(1 downto 0); 00158 TILE0_TXCHARDISPMODE1_IN : in std_logic_vector(1 downto 0); 00159 TILE0_TXCHARISK0_IN : in std_logic_vector(1 downto 0); 00160 TILE0_TXCHARISK1_IN : in std_logic_vector(1 downto 0); 00161 ------------------ Transmit Ports - TX Data Path interface ----------------- 00162 TILE0_TXDATA0_IN : in std_logic_vector(15 downto 0); 00163 TILE0_TXDATA1_IN : in std_logic_vector(15 downto 0); 00164 TILE0_TXUSRCLK0_IN : in std_logic; 00165 TILE0_TXUSRCLK1_IN : in std_logic; 00166 TILE0_TXUSRCLK20_IN : in std_logic; 00167 TILE0_TXUSRCLK21_IN : in std_logic; 00168 --------------- Transmit Ports - TX Driver and OOB signalling -------------- 00169 TILE0_TXN0_OUT : out std_logic; 00170 TILE0_TXN1_OUT : out std_logic; 00171 TILE0_TXP0_OUT : out std_logic; 00172 TILE0_TXP1_OUT : out std_logic; 00173 ----------------- Transmit Ports - TX Ports for PCI Express ---------------- 00174 TILE0_TXDETECTRX0_IN : in std_logic; 00175 TILE0_TXDETECTRX1_IN : in std_logic; 00176 TILE0_TXELECIDLE0_IN : in std_logic; 00177 TILE0_TXELECIDLE1_IN : in std_logic 00178 00179 00180 ); 00181 00182 00183 end GTPA1_DUAL_WRAPPER; 00184 00185 architecture RTL of GTPA1_DUAL_WRAPPER is 00186 attribute CORE_GENERATION_INFO : string; 00187 attribute CORE_GENERATION_INFO of RTL : architecture is "GTPA1_DUAL_WRAPPER,s6_gtpwizard_v1_4,{gtp0_protocol_file=pcie,gtp1_protocol_file=Use_GTP0_settings}"; 00188 00189 --***************************** Signal Declarations ***************************** 00190 00191 -- ground and tied_to_vcc_i signals 00192 signal tied_to_ground_i : std_logic; 00193 signal tied_to_ground_vec_i : std_logic_vector(63 downto 0); 00194 signal tied_to_vcc_i : std_logic; 00195 00196 signal tile0_plllkdet0_i : std_logic; 00197 signal tile0_plllkdet1_i : std_logic; 00198 00199 signal tile0_plllkdet0_i2 : std_logic; 00200 signal tile0_plllkdet1_i2 : std_logic; 00201 00202 00203 --*************************** Component Declarations ************************** 00204 00205 component GTPA1_DUAL_WRAPPER_TILE 00206 generic 00207 ( 00208 -- Simulation attributes 00209 TILE_SIM_GTPRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset 00210 TILE_CLK25_DIVIDER_0 : integer := 4; 00211 TILE_CLK25_DIVIDER_1 : integer := 4; 00212 TILE_PLL_DIVSEL_FB_0 : integer := 5; 00213 TILE_PLL_DIVSEL_FB_1 : integer := 5; 00214 TILE_PLL_DIVSEL_REF_0 : integer := 2; 00215 TILE_PLL_DIVSEL_REF_1 : integer := 2; 00216 -- 00217 TILE_PLL_SOURCE_0 : string := "PLL0"; 00218 TILE_PLL_SOURCE_1 : string := "PLL1" 00219 ); 00220 port 00221 ( 00222 ------------------------ Loopback and Powerdown Ports ---------------------- 00223 RXPOWERDOWN0_IN : in std_logic_vector(1 downto 0); 00224 RXPOWERDOWN1_IN : in std_logic_vector(1 downto 0); 00225 TXPOWERDOWN0_IN : in std_logic_vector(1 downto 0); 00226 TXPOWERDOWN1_IN : in std_logic_vector(1 downto 0); 00227 --------------------------------- PLL Ports -------------------------------- 00228 CLK00_IN : in std_logic; 00229 CLK01_IN : in std_logic; 00230 GTPRESET0_IN : in std_logic; 00231 GTPRESET1_IN : in std_logic; 00232 PLLLKDET0_OUT : out std_logic; 00233 PLLLKDET1_OUT : out std_logic; 00234 RESETDONE0_OUT : out std_logic; 00235 RESETDONE1_OUT : out std_logic; 00236 ----------------------- Receive Ports - 8b10b Decoder ---------------------- 00237 RXCHARISK0_OUT : out std_logic_vector(1 downto 0); 00238 RXCHARISK1_OUT : out std_logic_vector(1 downto 0); 00239 RXDISPERR0_OUT : out std_logic_vector(1 downto 0); 00240 RXDISPERR1_OUT : out std_logic_vector(1 downto 0); 00241 RXNOTINTABLE0_OUT : out std_logic_vector(1 downto 0); 00242 RXNOTINTABLE1_OUT : out std_logic_vector(1 downto 0); 00243 ---------------------- Receive Ports - Clock Correction -------------------- 00244 RXCLKCORCNT0_OUT : out std_logic_vector(2 downto 0); 00245 RXCLKCORCNT1_OUT : out std_logic_vector(2 downto 0); 00246 --------------- Receive Ports - Comma Detection and Alignment -------------- 00247 RXENMCOMMAALIGN0_IN : in std_logic; 00248 RXENMCOMMAALIGN1_IN : in std_logic; 00249 RXENPCOMMAALIGN0_IN : in std_logic; 00250 RXENPCOMMAALIGN1_IN : in std_logic; 00251 ------------------- Receive Ports - RX Data Path interface ----------------- 00252 RXDATA0_OUT : out std_logic_vector(15 downto 0); 00253 RXDATA1_OUT : out std_logic_vector(15 downto 0); 00254 RXRESET0_IN : in std_logic; 00255 RXRESET1_IN : in std_logic; 00256 RXUSRCLK0_IN : in std_logic; 00257 RXUSRCLK1_IN : in std_logic; 00258 RXUSRCLK20_IN : in std_logic; 00259 RXUSRCLK21_IN : in std_logic; 00260 ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ 00261 GATERXELECIDLE0_IN : in std_logic; 00262 GATERXELECIDLE1_IN : in std_logic; 00263 IGNORESIGDET0_IN : in std_logic; 00264 IGNORESIGDET1_IN : in std_logic; 00265 RXELECIDLE0_OUT : out std_logic; 00266 RXELECIDLE1_OUT : out std_logic; 00267 RXN0_IN : in std_logic; 00268 RXN1_IN : in std_logic; 00269 RXP0_IN : in std_logic; 00270 RXP1_IN : in std_logic; 00271 ----------- Receive Ports - RX Elastic Buffer and Phase Alignment ---------- 00272 RXSTATUS0_OUT : out std_logic_vector(2 downto 0); 00273 RXSTATUS1_OUT : out std_logic_vector(2 downto 0); 00274 -------------- Receive Ports - RX Pipe Control for PCI Express ------------- 00275 PHYSTATUS0_OUT : out std_logic; 00276 PHYSTATUS1_OUT : out std_logic; 00277 RXVALID0_OUT : out std_logic; 00278 RXVALID1_OUT : out std_logic; 00279 -------------------- Receive Ports - RX Polarity Control ------------------- 00280 RXPOLARITY0_IN : in std_logic; 00281 RXPOLARITY1_IN : in std_logic; 00282 ---------------------------- TX/RX Datapath Ports -------------------------- 00283 GTPCLKOUT0_OUT : out std_logic_vector(1 downto 0); 00284 GTPCLKOUT1_OUT : out std_logic_vector(1 downto 0); 00285 ------------------- Transmit Ports - 8b10b Encoder Control ----------------- 00286 TXCHARDISPMODE0_IN : in std_logic_vector(1 downto 0); 00287 TXCHARDISPMODE1_IN : in std_logic_vector(1 downto 0); 00288 TXCHARISK0_IN : in std_logic_vector(1 downto 0); 00289 TXCHARISK1_IN : in std_logic_vector(1 downto 0); 00290 ------------------ Transmit Ports - TX Data Path interface ----------------- 00291 TXDATA0_IN : in std_logic_vector(15 downto 0); 00292 TXDATA1_IN : in std_logic_vector(15 downto 0); 00293 TXUSRCLK0_IN : in std_logic; 00294 TXUSRCLK1_IN : in std_logic; 00295 TXUSRCLK20_IN : in std_logic; 00296 TXUSRCLK21_IN : in std_logic; 00297 --------------- Transmit Ports - TX Driver and OOB signalling -------------- 00298 TXN0_OUT : out std_logic; 00299 TXN1_OUT : out std_logic; 00300 TXP0_OUT : out std_logic; 00301 TXP1_OUT : out std_logic; 00302 ----------------- Transmit Ports - TX Ports for PCI Express ---------------- 00303 TXDETECTRX0_IN : in std_logic; 00304 TXDETECTRX1_IN : in std_logic; 00305 TXELECIDLE0_IN : in std_logic; 00306 TXELECIDLE1_IN : in std_logic 00307 00308 00309 ); 00310 end component; 00311 00312 00313 --********************************* Main Body of Code************************** 00314 00315 begin 00316 00317 tied_to_ground_i <= '0'; 00318 tied_to_ground_vec_i(63 downto 0) <= (others => '0'); 00319 tied_to_vcc_i <= '1'; 00320 00321 simulation : if WRAPPER_SIMULATION = 1 generate 00322 00323 TILE0_PLLLKDET0_OUT <= tile0_plllkdet0_i2; 00324 process 00325 begin 00326 wait until tile0_plllkdet0_i'event; 00327 if(tile0_plllkdet0_i = '1') then 00328 tile0_plllkdet0_i2 <= '1' after 100 ns; 00329 else 00330 tile0_plllkdet0_i2 <= tile0_plllkdet0_i; 00331 end if; 00332 end process; 00333 TILE0_PLLLKDET1_OUT <= tile0_plllkdet1_i2; 00334 process 00335 begin 00336 wait until tile0_plllkdet1_i'event; 00337 if(tile0_plllkdet1_i = '1') then 00338 tile0_plllkdet1_i2 <= '1' after 100 ns; 00339 else 00340 tile0_plllkdet1_i2 <= tile0_plllkdet1_i; 00341 end if; 00342 end process; 00343 00344 00345 00346 end generate simulation; 00347 00348 implementation : if WRAPPER_SIMULATION = 0 generate 00349 00350 TILE0_PLLLKDET0_OUT <= tile0_plllkdet0_i; 00351 TILE0_PLLLKDET1_OUT <= tile0_plllkdet1_i; 00352 00353 end generate implementation; 00354 00355 --------------------------- Tile Instances ------------------------------- 00356 00357 00358 --_________________________________________________________________________ 00359 --_________________________________________________________________________ 00360 --TILE0 (X0_Y0) 00361 00362 tile0_gtpa1_dual_wrapper_i : GTPA1_DUAL_WRAPPER_TILE 00363 generic map 00364 ( 00365 -- Simulation attributes 00366 TILE_SIM_GTPRESET_SPEEDUP => WRAPPER_SIM_GTPRESET_SPEEDUP, 00367 TILE_CLK25_DIVIDER_0 => WRAPPER_CLK25_DIVIDER_0, 00368 TILE_CLK25_DIVIDER_1 => WRAPPER_CLK25_DIVIDER_1, 00369 TILE_PLL_DIVSEL_FB_0 => WRAPPER_PLL_DIVSEL_FB_0, 00370 TILE_PLL_DIVSEL_FB_1 => WRAPPER_PLL_DIVSEL_FB_1, 00371 TILE_PLL_DIVSEL_REF_0 => WRAPPER_PLL_DIVSEL_REF_0, 00372 TILE_PLL_DIVSEL_REF_1 => WRAPPER_PLL_DIVSEL_REF_1, 00373 00374 -- 00375 TILE_PLL_SOURCE_0 => "PLL0", 00376 TILE_PLL_SOURCE_1 => "PLL1" 00377 ) 00378 port map 00379 ( 00380 ------------------------ Loopback and Powerdown Ports ---------------------- 00381 RXPOWERDOWN0_IN => TILE0_RXPOWERDOWN0_IN, 00382 RXPOWERDOWN1_IN => TILE0_RXPOWERDOWN1_IN, 00383 TXPOWERDOWN0_IN => TILE0_TXPOWERDOWN0_IN, 00384 TXPOWERDOWN1_IN => TILE0_TXPOWERDOWN1_IN, 00385 --------------------------------- PLL Ports -------------------------------- 00386 CLK00_IN => TILE0_CLK00_IN, 00387 CLK01_IN => TILE0_CLK01_IN, 00388 GTPRESET0_IN => TILE0_GTPRESET0_IN, 00389 GTPRESET1_IN => TILE0_GTPRESET1_IN, 00390 PLLLKDET0_OUT => tile0_plllkdet0_i, 00391 PLLLKDET1_OUT => tile0_plllkdet1_i, 00392 RESETDONE0_OUT => TILE0_RESETDONE0_OUT, 00393 RESETDONE1_OUT => TILE0_RESETDONE1_OUT, 00394 ----------------------- Receive Ports - 8b10b Decoder ---------------------- 00395 RXCHARISK0_OUT => TILE0_RXCHARISK0_OUT, 00396 RXCHARISK1_OUT => TILE0_RXCHARISK1_OUT, 00397 RXDISPERR0_OUT => TILE0_RXDISPERR0_OUT, 00398 RXDISPERR1_OUT => TILE0_RXDISPERR1_OUT, 00399 RXNOTINTABLE0_OUT => TILE0_RXNOTINTABLE0_OUT, 00400 RXNOTINTABLE1_OUT => TILE0_RXNOTINTABLE1_OUT, 00401 ---------------------- Receive Ports - Clock Correction -------------------- 00402 RXCLKCORCNT0_OUT => TILE0_RXCLKCORCNT0_OUT, 00403 RXCLKCORCNT1_OUT => TILE0_RXCLKCORCNT1_OUT, 00404 --------------- Receive Ports - Comma Detection and Alignment -------------- 00405 RXENMCOMMAALIGN0_IN => TILE0_RXENMCOMMAALIGN0_IN, 00406 RXENMCOMMAALIGN1_IN => TILE0_RXENMCOMMAALIGN1_IN, 00407 RXENPCOMMAALIGN0_IN => TILE0_RXENPCOMMAALIGN0_IN, 00408 RXENPCOMMAALIGN1_IN => TILE0_RXENPCOMMAALIGN1_IN, 00409 ------------------- Receive Ports - RX Data Path interface ----------------- 00410 RXDATA0_OUT => TILE0_RXDATA0_OUT, 00411 RXDATA1_OUT => TILE0_RXDATA1_OUT, 00412 RXRESET0_IN => TILE0_RXRESET0_IN, 00413 RXRESET1_IN => TILE0_RXRESET1_IN, 00414 RXUSRCLK0_IN => TILE0_RXUSRCLK0_IN, 00415 RXUSRCLK1_IN => TILE0_RXUSRCLK1_IN, 00416 RXUSRCLK20_IN => TILE0_RXUSRCLK20_IN, 00417 RXUSRCLK21_IN => TILE0_RXUSRCLK21_IN, 00418 ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ 00419 GATERXELECIDLE0_IN => TILE0_GATERXELECIDLE0_IN, 00420 GATERXELECIDLE1_IN => TILE0_GATERXELECIDLE1_IN, 00421 IGNORESIGDET0_IN => TILE0_IGNORESIGDET0_IN, 00422 IGNORESIGDET1_IN => TILE0_IGNORESIGDET1_IN, 00423 RXELECIDLE0_OUT => TILE0_RXELECIDLE0_OUT, 00424 RXELECIDLE1_OUT => TILE0_RXELECIDLE1_OUT, 00425 RXN0_IN => TILE0_RXN0_IN, 00426 RXN1_IN => TILE0_RXN1_IN, 00427 RXP0_IN => TILE0_RXP0_IN, 00428 RXP1_IN => TILE0_RXP1_IN, 00429 ----------- Receive Ports - RX Elastic Buffer and Phase Alignment ---------- 00430 RXSTATUS0_OUT => TILE0_RXSTATUS0_OUT, 00431 RXSTATUS1_OUT => TILE0_RXSTATUS1_OUT, 00432 -------------- Receive Ports - RX Pipe Control for PCI Express ------------- 00433 PHYSTATUS0_OUT => TILE0_PHYSTATUS0_OUT, 00434 PHYSTATUS1_OUT => TILE0_PHYSTATUS1_OUT, 00435 RXVALID0_OUT => TILE0_RXVALID0_OUT, 00436 RXVALID1_OUT => TILE0_RXVALID1_OUT, 00437 -------------------- Receive Ports - RX Polarity Control ------------------- 00438 RXPOLARITY0_IN => TILE0_RXPOLARITY0_IN, 00439 RXPOLARITY1_IN => TILE0_RXPOLARITY1_IN, 00440 ---------------------------- TX/RX Datapath Ports -------------------------- 00441 GTPCLKOUT0_OUT => TILE0_GTPCLKOUT0_OUT, 00442 GTPCLKOUT1_OUT => TILE0_GTPCLKOUT1_OUT, 00443 ------------------- Transmit Ports - 8b10b Encoder Control ----------------- 00444 TXCHARDISPMODE0_IN => TILE0_TXCHARDISPMODE0_IN, 00445 TXCHARDISPMODE1_IN => TILE0_TXCHARDISPMODE1_IN, 00446 TXCHARISK0_IN => TILE0_TXCHARISK0_IN, 00447 TXCHARISK1_IN => TILE0_TXCHARISK1_IN, 00448 ------------------ Transmit Ports - TX Data Path interface ----------------- 00449 TXDATA0_IN => TILE0_TXDATA0_IN, 00450 TXDATA1_IN => TILE0_TXDATA1_IN, 00451 TXUSRCLK0_IN => TILE0_TXUSRCLK0_IN, 00452 TXUSRCLK1_IN => TILE0_TXUSRCLK1_IN, 00453 TXUSRCLK20_IN => TILE0_TXUSRCLK20_IN, 00454 TXUSRCLK21_IN => TILE0_TXUSRCLK21_IN, 00455 --------------- Transmit Ports - TX Driver and OOB signalling -------------- 00456 TXN0_OUT => TILE0_TXN0_OUT, 00457 TXN1_OUT => TILE0_TXN1_OUT, 00458 TXP0_OUT => TILE0_TXP0_OUT, 00459 TXP1_OUT => TILE0_TXP1_OUT, 00460 ----------------- Transmit Ports - TX Ports for PCI Express ---------------- 00461 TXDETECTRX0_IN => TILE0_TXDETECTRX0_IN, 00462 TXDETECTRX1_IN => TILE0_TXDETECTRX1_IN, 00463 TXELECIDLE0_IN => TILE0_TXELECIDLE0_IN, 00464 TXELECIDLE1_IN => TILE0_TXELECIDLE1_IN 00465 00466 ); 00467 00468 00469 end RTL;
1.7.4