Граф наследования:GTPA1_DUAL_WRAPPER:
Architectures | |
| RTL | Architecture |
Libraries | |
| ieee | |
| UNISIM | |
Packages | |
| std_logic_1164 | |
| numeric_std | |
| VCOMPONENTS | |
Generics | |
| WRAPPER_SIM_GTPRESET_SPEEDUP | integer := 0 |
| WRAPPER_CLK25_DIVIDER_0 | integer := 4 |
| WRAPPER_CLK25_DIVIDER_1 | integer := 4 |
| WRAPPER_PLL_DIVSEL_FB_0 | integer := 5 |
| WRAPPER_PLL_DIVSEL_FB_1 | integer := 5 |
| WRAPPER_PLL_DIVSEL_REF_0 | integer := 2 |
| WRAPPER_PLL_DIVSEL_REF_1 | integer := 2 |
| WRAPPER_SIMULATION | integer := 0 |
Ports | |
| TILE0_RXPOWERDOWN0_IN | in std_logic_vector ( 1 downto 0 ) |
| TILE0_RXPOWERDOWN1_IN | in std_logic_vector ( 1 downto 0 ) |
| TILE0_TXPOWERDOWN0_IN | in std_logic_vector ( 1 downto 0 ) |
| TILE0_TXPOWERDOWN1_IN | in std_logic_vector ( 1 downto 0 ) |
| TILE0_CLK00_IN | in std_logic |
| TILE0_CLK01_IN | in std_logic |
| TILE0_GTPRESET0_IN | in std_logic |
| TILE0_GTPRESET1_IN | in std_logic |
| TILE0_PLLLKDET0_OUT | out std_logic |
| TILE0_PLLLKDET1_OUT | out std_logic |
| TILE0_RESETDONE0_OUT | out std_logic |
| TILE0_RESETDONE1_OUT | out std_logic |
| TILE0_RXCHARISK0_OUT | out std_logic_vector ( 1 downto 0 ) |
| TILE0_RXCHARISK1_OUT | out std_logic_vector ( 1 downto 0 ) |
| TILE0_RXDISPERR0_OUT | out std_logic_vector ( 1 downto 0 ) |
| TILE0_RXDISPERR1_OUT | out std_logic_vector ( 1 downto 0 ) |
| TILE0_RXNOTINTABLE0_OUT | out std_logic_vector ( 1 downto 0 ) |
| TILE0_RXNOTINTABLE1_OUT | out std_logic_vector ( 1 downto 0 ) |
| TILE0_RXCLKCORCNT0_OUT | out std_logic_vector ( 2 downto 0 ) |
| TILE0_RXCLKCORCNT1_OUT | out std_logic_vector ( 2 downto 0 ) |
| TILE0_RXENMCOMMAALIGN0_IN | in std_logic |
| TILE0_RXENMCOMMAALIGN1_IN | in std_logic |
| TILE0_RXENPCOMMAALIGN0_IN | in std_logic |
| TILE0_RXENPCOMMAALIGN1_IN | in std_logic |
| TILE0_RXDATA0_OUT | out std_logic_vector ( 15 downto 0 ) |
| TILE0_RXDATA1_OUT | out std_logic_vector ( 15 downto 0 ) |
| TILE0_RXRESET0_IN | in std_logic |
| TILE0_RXRESET1_IN | in std_logic |
| TILE0_RXUSRCLK0_IN | in std_logic |
| TILE0_RXUSRCLK1_IN | in std_logic |
| TILE0_RXUSRCLK20_IN | in std_logic |
| TILE0_RXUSRCLK21_IN | in std_logic |
| TILE0_GATERXELECIDLE0_IN | in std_logic |
| TILE0_GATERXELECIDLE1_IN | in std_logic |
| TILE0_IGNORESIGDET0_IN | in std_logic |
| TILE0_IGNORESIGDET1_IN | in std_logic |
| TILE0_RXELECIDLE0_OUT | out std_logic |
| TILE0_RXELECIDLE1_OUT | out std_logic |
| TILE0_RXN0_IN | in std_logic |
| TILE0_RXN1_IN | in std_logic |
| TILE0_RXP0_IN | in std_logic |
| TILE0_RXP1_IN | in std_logic |
| TILE0_RXSTATUS0_OUT | out std_logic_vector ( 2 downto 0 ) |
| TILE0_RXSTATUS1_OUT | out std_logic_vector ( 2 downto 0 ) |
| TILE0_PHYSTATUS0_OUT | out std_logic |
| TILE0_PHYSTATUS1_OUT | out std_logic |
| TILE0_RXVALID0_OUT | out std_logic |
| TILE0_RXVALID1_OUT | out std_logic |
| TILE0_RXPOLARITY0_IN | in std_logic |
| TILE0_RXPOLARITY1_IN | in std_logic |
| TILE0_GTPCLKOUT0_OUT | out std_logic_vector ( 1 downto 0 ) |
| TILE0_GTPCLKOUT1_OUT | out std_logic_vector ( 1 downto 0 ) |
| TILE0_TXCHARDISPMODE0_IN | in std_logic_vector ( 1 downto 0 ) |
| TILE0_TXCHARDISPMODE1_IN | in std_logic_vector ( 1 downto 0 ) |
| TILE0_TXCHARISK0_IN | in std_logic_vector ( 1 downto 0 ) |
| TILE0_TXCHARISK1_IN | in std_logic_vector ( 1 downto 0 ) |
| TILE0_TXDATA0_IN | in std_logic_vector ( 15 downto 0 ) |
| TILE0_TXDATA1_IN | in std_logic_vector ( 15 downto 0 ) |
| TILE0_TXUSRCLK0_IN | in std_logic |
| TILE0_TXUSRCLK1_IN | in std_logic |
| TILE0_TXUSRCLK20_IN | in std_logic |
| TILE0_TXUSRCLK21_IN | in std_logic |
| TILE0_TXN0_OUT | out std_logic |
| TILE0_TXN1_OUT | out std_logic |
| TILE0_TXP0_OUT | out std_logic |
| TILE0_TXP1_OUT | out std_logic |
| TILE0_TXDETECTRX0_IN | in std_logic |
| TILE0_TXDETECTRX1_IN | in std_logic |
| TILE0_TXELECIDLE0_IN | in std_logic |
| TILE0_TXELECIDLE1_IN | in std_logic |
Подробное описание
См. определение в файле gtpa1_dual_wrapper.vhd строка 73
Объявления и описания членов класса находятся в файле:
- pcie_src/pcie_core64_m1/source_s6/gtpa1_dual_wrapper.vhd
