Граф наследования:GTPA1_DUAL_WRAPPER_TILE:
Architectures | |
| RTL | Architecture |
Libraries | |
| ieee | |
| UNISIM | |
Packages | |
| std_logic_1164 | |
| numeric_std | |
| VCOMPONENTS | |
Generics | |
| TILE_SIM_GTPRESET_SPEEDUP | integer := 0 |
| TILE_CLK25_DIVIDER_0 | integer := 4 |
| TILE_CLK25_DIVIDER_1 | integer := 4 |
| TILE_PLL_DIVSEL_FB_0 | integer := 5 |
| TILE_PLL_DIVSEL_FB_1 | integer := 5 |
| TILE_PLL_DIVSEL_REF_0 | integer := 2 |
| TILE_PLL_DIVSEL_REF_1 | integer := 2 |
| TILE_PLL_SOURCE_0 | string := " pll0 " |
| TILE_PLL_SOURCE_1 | string := " pll1 " |
Ports | |
| RXPOWERDOWN0_IN | in std_logic_vector ( 1 downto 0 ) |
| RXPOWERDOWN1_IN | in std_logic_vector ( 1 downto 0 ) |
| TXPOWERDOWN0_IN | in std_logic_vector ( 1 downto 0 ) |
| TXPOWERDOWN1_IN | in std_logic_vector ( 1 downto 0 ) |
| CLK00_IN | in std_logic |
| CLK01_IN | in std_logic |
| GTPRESET0_IN | in std_logic |
| GTPRESET1_IN | in std_logic |
| PLLLKDET0_OUT | out std_logic |
| PLLLKDET1_OUT | out std_logic |
| RESETDONE0_OUT | out std_logic |
| RESETDONE1_OUT | out std_logic |
| RXCHARISK0_OUT | out std_logic_vector ( 1 downto 0 ) |
| RXCHARISK1_OUT | out std_logic_vector ( 1 downto 0 ) |
| RXDISPERR0_OUT | out std_logic_vector ( 1 downto 0 ) |
| RXDISPERR1_OUT | out std_logic_vector ( 1 downto 0 ) |
| RXNOTINTABLE0_OUT | out std_logic_vector ( 1 downto 0 ) |
| RXNOTINTABLE1_OUT | out std_logic_vector ( 1 downto 0 ) |
| RXCLKCORCNT0_OUT | out std_logic_vector ( 2 downto 0 ) |
| RXCLKCORCNT1_OUT | out std_logic_vector ( 2 downto 0 ) |
| RXENMCOMMAALIGN0_IN | in std_logic |
| RXENMCOMMAALIGN1_IN | in std_logic |
| RXENPCOMMAALIGN0_IN | in std_logic |
| RXENPCOMMAALIGN1_IN | in std_logic |
| RXDATA0_OUT | out std_logic_vector ( 15 downto 0 ) |
| RXDATA1_OUT | out std_logic_vector ( 15 downto 0 ) |
| RXRESET0_IN | in std_logic |
| RXRESET1_IN | in std_logic |
| RXUSRCLK0_IN | in std_logic |
| RXUSRCLK1_IN | in std_logic |
| RXUSRCLK20_IN | in std_logic |
| RXUSRCLK21_IN | in std_logic |
| GATERXELECIDLE0_IN | in std_logic |
| GATERXELECIDLE1_IN | in std_logic |
| IGNORESIGDET0_IN | in std_logic |
| IGNORESIGDET1_IN | in std_logic |
| RXELECIDLE0_OUT | out std_logic |
| RXELECIDLE1_OUT | out std_logic |
| RXN0_IN | in std_logic |
| RXN1_IN | in std_logic |
| RXP0_IN | in std_logic |
| RXP1_IN | in std_logic |
| RXSTATUS0_OUT | out std_logic_vector ( 2 downto 0 ) |
| RXSTATUS1_OUT | out std_logic_vector ( 2 downto 0 ) |
| PHYSTATUS0_OUT | out std_logic |
| PHYSTATUS1_OUT | out std_logic |
| RXVALID0_OUT | out std_logic |
| RXVALID1_OUT | out std_logic |
| RXPOLARITY0_IN | in std_logic |
| RXPOLARITY1_IN | in std_logic |
| GTPCLKOUT0_OUT | out std_logic_vector ( 1 downto 0 ) |
| GTPCLKOUT1_OUT | out std_logic_vector ( 1 downto 0 ) |
| TXCHARDISPMODE0_IN | in std_logic_vector ( 1 downto 0 ) |
| TXCHARDISPMODE1_IN | in std_logic_vector ( 1 downto 0 ) |
| TXCHARISK0_IN | in std_logic_vector ( 1 downto 0 ) |
| TXCHARISK1_IN | in std_logic_vector ( 1 downto 0 ) |
| TXDATA0_IN | in std_logic_vector ( 15 downto 0 ) |
| TXDATA1_IN | in std_logic_vector ( 15 downto 0 ) |
| TXUSRCLK0_IN | in std_logic |
| TXUSRCLK1_IN | in std_logic |
| TXUSRCLK20_IN | in std_logic |
| TXUSRCLK21_IN | in std_logic |
| TXN0_OUT | out std_logic |
| TXN1_OUT | out std_logic |
| TXP0_OUT | out std_logic |
| TXP1_OUT | out std_logic |
| TXDETECTRX0_IN | in std_logic |
| TXDETECTRX1_IN | in std_logic |
| TXELECIDLE0_IN | in std_logic |
| TXELECIDLE1_IN | in std_logic |
Подробное описание
См. определение в файле gtpa1_dual_wrapper_tile.vhd строка 72
Объявления и описания членов класса находятся в файле:
- pcie_src/pcie_core64_m1/source_s6/gtpa1_dual_wrapper_tile.vhd
