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DS_DMA
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00001 ------------------------------------------------------------------------------- 00002 -- ____ ____ 00003 -- / /\/ / 00004 -- /___/ \ / Vendor: Xilinx 00005 -- \ \ \/ Version : 1.7 00006 -- \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard 00007 -- / / Filename : gtpa1_dual_wrapper_tile.vhd 00008 -- /___/ /\ Timestamp : 00009 -- \ \ / \ 00010 -- \___\/\___\ 00011 -- 00012 -- 00013 -- Module GTPA1_DUAL_WRAPPER_TILE (a GTPA1_DUAL Tile Wrapper) 00014 -- Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard 00015 -- 00016 -- 00017 -- (c) Copyright 2009 Xilinx, Inc. All rights reserved. 00018 -- 00019 -- This file contains confidential and proprietary information 00020 -- of Xilinx, Inc. and is protected under U.S. and 00021 -- international copyright and other intellectual property 00022 -- laws. 00023 -- 00024 -- DISCLAIMER 00025 -- This disclaimer is not a license and does not grant any 00026 -- rights to the materials distributed herewith. Except as 00027 -- otherwise provided in a valid license issued to you by 00028 -- Xilinx, and to the maximum extent permitted by applicable 00029 -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 00030 -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 00031 -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 00032 -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 00033 -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 00034 -- (2) Xilinx shall not be liable (whether in contract or tort, 00035 -- including negligence, or under any other theory of 00036 -- liability) for any loss or damage of any kind or nature 00037 -- related to, arising under or in connection with these 00038 -- materials, including for any direct, or any indirect, 00039 -- special, incidental, or consequential loss or damage 00040 -- (including loss of data, profits, goodwill, or any type of 00041 -- loss or damage suffered as a result of any action brought 00042 -- by a third party) even if such damage or loss was 00043 -- reasonably foreseeable or Xilinx had been advised of the 00044 -- possibility of the same. 00045 -- 00046 -- CRITICAL APPLICATIONS 00047 -- Xilinx products are not designed or intended to be fail- 00048 -- safe, or for use in any application requiring fail-safe 00049 -- performance, such as life-support or safety devices or 00050 -- systems, Class III medical devices, nuclear facilities, 00051 -- applications related to the deployment of airbags, or any 00052 -- other applications that could lead to death, personal 00053 -- injury, or severe property or environmental damage 00054 -- (individually and collectively, "Critical 00055 -- Applications"). Customer assumes the sole risk and 00056 -- liability of any use of Xilinx products in Critical 00057 -- Applications, subject only to applicable laws and 00058 -- regulations governing limitations on product liability. 00059 -- 00060 -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 00061 -- PART OF THIS FILE AT ALL TIMES. 00062 00063 00064 library ieee; 00065 use ieee.std_logic_1164.all; 00066 use ieee.numeric_std.all; 00067 library UNISIM; 00068 use UNISIM.VCOMPONENTS.ALL; 00069 00070 --***************************** Entity Declaration **************************** 00071 00072 entity GTPA1_DUAL_WRAPPER_TILE is 00073 generic 00074 ( 00075 -- Simulation attributes 00076 TILE_SIM_GTPRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset 00077 TILE_CLK25_DIVIDER_0 : integer := 4; 00078 TILE_CLK25_DIVIDER_1 : integer := 4; 00079 TILE_PLL_DIVSEL_FB_0 : integer := 5; 00080 TILE_PLL_DIVSEL_FB_1 : integer := 5; 00081 TILE_PLL_DIVSEL_REF_0 : integer := 2; 00082 TILE_PLL_DIVSEL_REF_1 : integer := 2; 00083 00084 -- 00085 TILE_PLL_SOURCE_0 : string := "PLL0"; 00086 TILE_PLL_SOURCE_1 : string := "PLL1" 00087 ); 00088 port 00089 ( 00090 ------------------------ Loopback and Powerdown Ports ---------------------- 00091 RXPOWERDOWN0_IN : in std_logic_vector(1 downto 0); 00092 RXPOWERDOWN1_IN : in std_logic_vector(1 downto 0); 00093 TXPOWERDOWN0_IN : in std_logic_vector(1 downto 0); 00094 TXPOWERDOWN1_IN : in std_logic_vector(1 downto 0); 00095 --------------------------------- PLL Ports -------------------------------- 00096 CLK00_IN : in std_logic; 00097 CLK01_IN : in std_logic; 00098 GTPRESET0_IN : in std_logic; 00099 GTPRESET1_IN : in std_logic; 00100 PLLLKDET0_OUT : out std_logic; 00101 PLLLKDET1_OUT : out std_logic; 00102 RESETDONE0_OUT : out std_logic; 00103 RESETDONE1_OUT : out std_logic; 00104 ----------------------- Receive Ports - 8b10b Decoder ---------------------- 00105 RXCHARISK0_OUT : out std_logic_vector(1 downto 0); 00106 RXCHARISK1_OUT : out std_logic_vector(1 downto 0); 00107 RXDISPERR0_OUT : out std_logic_vector(1 downto 0); 00108 RXDISPERR1_OUT : out std_logic_vector(1 downto 0); 00109 RXNOTINTABLE0_OUT : out std_logic_vector(1 downto 0); 00110 RXNOTINTABLE1_OUT : out std_logic_vector(1 downto 0); 00111 ---------------------- Receive Ports - Clock Correction -------------------- 00112 RXCLKCORCNT0_OUT : out std_logic_vector(2 downto 0); 00113 RXCLKCORCNT1_OUT : out std_logic_vector(2 downto 0); 00114 --------------- Receive Ports - Comma Detection and Alignment -------------- 00115 RXENMCOMMAALIGN0_IN : in std_logic; 00116 RXENMCOMMAALIGN1_IN : in std_logic; 00117 RXENPCOMMAALIGN0_IN : in std_logic; 00118 RXENPCOMMAALIGN1_IN : in std_logic; 00119 ------------------- Receive Ports - RX Data Path interface ----------------- 00120 RXDATA0_OUT : out std_logic_vector(15 downto 0); 00121 RXDATA1_OUT : out std_logic_vector(15 downto 0); 00122 RXRESET0_IN : in std_logic; 00123 RXRESET1_IN : in std_logic; 00124 RXUSRCLK0_IN : in std_logic; 00125 RXUSRCLK1_IN : in std_logic; 00126 RXUSRCLK20_IN : in std_logic; 00127 RXUSRCLK21_IN : in std_logic; 00128 ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ 00129 GATERXELECIDLE0_IN : in std_logic; 00130 GATERXELECIDLE1_IN : in std_logic; 00131 IGNORESIGDET0_IN : in std_logic; 00132 IGNORESIGDET1_IN : in std_logic; 00133 RXELECIDLE0_OUT : out std_logic; 00134 RXELECIDLE1_OUT : out std_logic; 00135 RXN0_IN : in std_logic; 00136 RXN1_IN : in std_logic; 00137 RXP0_IN : in std_logic; 00138 RXP1_IN : in std_logic; 00139 ----------- Receive Ports - RX Elastic Buffer and Phase Alignment ---------- 00140 RXSTATUS0_OUT : out std_logic_vector(2 downto 0); 00141 RXSTATUS1_OUT : out std_logic_vector(2 downto 0); 00142 -------------- Receive Ports - RX Pipe Control for PCI Express ------------- 00143 PHYSTATUS0_OUT : out std_logic; 00144 PHYSTATUS1_OUT : out std_logic; 00145 RXVALID0_OUT : out std_logic; 00146 RXVALID1_OUT : out std_logic; 00147 -------------------- Receive Ports - RX Polarity Control ------------------- 00148 RXPOLARITY0_IN : in std_logic; 00149 RXPOLARITY1_IN : in std_logic; 00150 ---------------------------- TX/RX Datapath Ports -------------------------- 00151 GTPCLKOUT0_OUT : out std_logic_vector(1 downto 0); 00152 GTPCLKOUT1_OUT : out std_logic_vector(1 downto 0); 00153 ------------------- Transmit Ports - 8b10b Encoder Control ----------------- 00154 TXCHARDISPMODE0_IN : in std_logic_vector(1 downto 0); 00155 TXCHARDISPMODE1_IN : in std_logic_vector(1 downto 0); 00156 TXCHARISK0_IN : in std_logic_vector(1 downto 0); 00157 TXCHARISK1_IN : in std_logic_vector(1 downto 0); 00158 ------------------ Transmit Ports - TX Data Path interface ----------------- 00159 TXDATA0_IN : in std_logic_vector(15 downto 0); 00160 TXDATA1_IN : in std_logic_vector(15 downto 0); 00161 TXUSRCLK0_IN : in std_logic; 00162 TXUSRCLK1_IN : in std_logic; 00163 TXUSRCLK20_IN : in std_logic; 00164 TXUSRCLK21_IN : in std_logic; 00165 --------------- Transmit Ports - TX Driver and OOB signalling -------------- 00166 TXN0_OUT : out std_logic; 00167 TXN1_OUT : out std_logic; 00168 TXP0_OUT : out std_logic; 00169 TXP1_OUT : out std_logic; 00170 ----------------- Transmit Ports - TX Ports for PCI Express ---------------- 00171 TXDETECTRX0_IN : in std_logic; 00172 TXDETECTRX1_IN : in std_logic; 00173 TXELECIDLE0_IN : in std_logic; 00174 TXELECIDLE1_IN : in std_logic 00175 00176 00177 ); 00178 00179 00180 end GTPA1_DUAL_WRAPPER_TILE; 00181 00182 architecture RTL of GTPA1_DUAL_WRAPPER_TILE is 00183 00184 --**************************** Signal Declarations **************************** 00185 00186 -- ground and tied_to_vcc_i signals 00187 signal tied_to_ground_i : std_logic; 00188 signal tied_to_ground_vec_i : std_logic_vector(63 downto 0); 00189 signal tied_to_vcc_i : std_logic; 00190 signal tied_to_vcc_vec_i : std_logic_vector(63 downto 0); 00191 00192 00193 00194 -- RX Datapath signals 00195 signal rxdata0_i : std_logic_vector(31 downto 0); 00196 signal rxchariscomma0_float_i : std_logic_vector(1 downto 0); 00197 signal rxcharisk0_float_i : std_logic_vector(1 downto 0); 00198 signal rxdisperr0_float_i : std_logic_vector(1 downto 0); 00199 signal rxnotintable0_float_i : std_logic_vector(1 downto 0); 00200 signal rxrundisp0_float_i : std_logic_vector(1 downto 0); 00201 00202 00203 -- TX Datapath signals 00204 signal txdata0_i : std_logic_vector(31 downto 0); 00205 signal txkerr0_float_i : std_logic_vector(1 downto 0); 00206 signal txrundisp0_float_i : std_logic_vector(1 downto 0); 00207 00208 00209 -- RX Datapath signals 00210 signal rxdata1_i : std_logic_vector(31 downto 0); 00211 signal rxchariscomma1_float_i : std_logic_vector(1 downto 0); 00212 signal rxcharisk1_float_i : std_logic_vector(1 downto 0); 00213 signal rxdisperr1_float_i : std_logic_vector(1 downto 0); 00214 signal rxnotintable1_float_i : std_logic_vector(1 downto 0); 00215 signal rxrundisp1_float_i : std_logic_vector(1 downto 0); 00216 00217 00218 -- TX Datapath signals 00219 signal txdata1_i : std_logic_vector(31 downto 0); 00220 signal txkerr1_float_i : std_logic_vector(1 downto 0); 00221 signal txrundisp1_float_i : std_logic_vector(1 downto 0); 00222 00223 --******************************** Main Body of Code*************************** 00224 00225 begin 00226 00227 --------------------------- Static signal Assignments --------------------- 00228 00229 tied_to_ground_i <= '0'; 00230 tied_to_ground_vec_i(63 downto 0) <= (others => '0'); 00231 tied_to_vcc_i <= '1'; 00232 tied_to_vcc_vec_i(63 downto 0) <= (others => '1'); 00233 00234 ------------------- GTP Datapath byte mapping ----------------- 00235 00236 -- The GTP provides little endian data (first byte received on RXDATA(7 downto 0)) 00237 RXDATA0_OUT <= rxdata0_i(15 downto 0); 00238 00239 txdata0_i <= (tied_to_ground_vec_i(15 downto 0) & TXDATA0_IN); 00240 00241 -- The GTP provides little endian data (first byte received on RXDATA(7 downto 0)) 00242 RXDATA1_OUT <= rxdata1_i(15 downto 0); 00243 00244 txdata1_i <= (tied_to_ground_vec_i(15 downto 0) & TXDATA1_IN); 00245 00246 00247 00248 ----------------------------- GTPA1_DUAL Instance -------------------------- 00249 00250 gtpa1_dual_i:GTPA1_DUAL 00251 generic map 00252 ( 00253 00254 --_______________________ Simulation-Only Attributes ___________________ 00255 00256 SIM_RECEIVER_DETECT_PASS => (TRUE), 00257 SIM_TX_ELEC_IDLE_LEVEL => ("Z"), 00258 SIM_VERSION => ("2.0"), 00259 SIM_REFCLK0_SOURCE => ("000"), 00260 SIM_REFCLK1_SOURCE => ("000"), 00261 SIM_GTPRESET_SPEEDUP => (TILE_SIM_GTPRESET_SPEEDUP), 00262 CLK25_DIVIDER_0 => (TILE_CLK25_DIVIDER_0), 00263 CLK25_DIVIDER_1 => (TILE_CLK25_DIVIDER_1), 00264 PLL_DIVSEL_FB_0 => (TILE_PLL_DIVSEL_FB_0), 00265 PLL_DIVSEL_FB_1 => (TILE_PLL_DIVSEL_FB_1), 00266 PLL_DIVSEL_REF_0 => (TILE_PLL_DIVSEL_REF_0), 00267 PLL_DIVSEL_REF_1 => (TILE_PLL_DIVSEL_REF_1), 00268 00269 00270 --PLL Attributes 00271 CLKINDC_B_0 => (TRUE), 00272 CLKRCV_TRST_0 => (TRUE), 00273 OOB_CLK_DIVIDER_0 => (4), 00274 PLL_COM_CFG_0 => (x"21680a"), 00275 PLL_CP_CFG_0 => (x"00"), 00276 PLL_RXDIVSEL_OUT_0 => (1), 00277 PLL_SATA_0 => (FALSE), 00278 PLL_SOURCE_0 => (TILE_PLL_SOURCE_0), 00279 PLL_TXDIVSEL_OUT_0 => (1), 00280 PLLLKDET_CFG_0 => ("111"), 00281 00282 -- 00283 CLKINDC_B_1 => (TRUE), 00284 CLKRCV_TRST_1 => (TRUE), 00285 OOB_CLK_DIVIDER_1 => (4), 00286 PLL_COM_CFG_1 => (x"21680a"), 00287 PLL_CP_CFG_1 => (x"00"), 00288 PLL_RXDIVSEL_OUT_1 => (1), 00289 PLL_SATA_1 => (FALSE), 00290 PLL_SOURCE_1 => (TILE_PLL_SOURCE_1), 00291 PLL_TXDIVSEL_OUT_1 => (1), 00292 PLLLKDET_CFG_1 => ("111"), 00293 PMA_COM_CFG_EAST => (x"000008000"), 00294 PMA_COM_CFG_WEST => (x"00000a000"), 00295 TST_ATTR_0 => (x"00000000"), 00296 TST_ATTR_1 => (x"00000000"), 00297 00298 --TX Interface Attributes 00299 CLK_OUT_GTP_SEL_0 => ("REFCLKPLL0"), 00300 TX_TDCC_CFG_0 => ("11"), 00301 CLK_OUT_GTP_SEL_1 => ("REFCLKPLL1"), 00302 TX_TDCC_CFG_1 => ("11"), 00303 00304 --TX Buffer and Phase Alignment Attributes 00305 PMA_TX_CFG_0 => (x"00082"), 00306 TX_BUFFER_USE_0 => (TRUE), 00307 TX_XCLK_SEL_0 => ("TXOUT"), 00308 TXRX_INVERT_0 => ("011"), 00309 PMA_TX_CFG_1 => (x"00082"), 00310 TX_BUFFER_USE_1 => (TRUE), 00311 TX_XCLK_SEL_1 => ("TXOUT"), 00312 TXRX_INVERT_1 => ("011"), 00313 00314 --TX Driver and OOB signalling Attributes 00315 CM_TRIM_0 => ("00"), 00316 TX_IDLE_DELAY_0 => ("010"), 00317 CM_TRIM_1 => ("00"), 00318 TX_IDLE_DELAY_1 => ("010"), 00319 00320 --TX PIPE/SATA Attributes 00321 COM_BURST_VAL_0 => ("1111"), 00322 COM_BURST_VAL_1 => ("1111"), 00323 00324 --RX Driver,OOB signalling,Coupling and Eq,CDR Attributes 00325 AC_CAP_DIS_0 => (FALSE), 00326 OOBDETECT_THRESHOLD_0 => ("111"), 00327 PMA_CDR_SCAN_0 => (x"6404040"), 00328 PMA_RX_CFG_0 => (x"05ce089"), 00329 PMA_RXSYNC_CFG_0 => (x"00"), 00330 RCV_TERM_GND_0 => (TRUE), 00331 RCV_TERM_VTTRX_0 => (FALSE), 00332 RXEQ_CFG_0 => ("01111011"), 00333 TERMINATION_CTRL_0 => ("10100"), 00334 TERMINATION_OVRD_0 => (FALSE), 00335 TX_DETECT_RX_CFG_0 => (x"1832"), 00336 AC_CAP_DIS_1 => (FALSE), 00337 OOBDETECT_THRESHOLD_1 => ("111"), 00338 PMA_CDR_SCAN_1 => (x"6404040"), 00339 PMA_RX_CFG_1 => (x"05ce089"), 00340 PMA_RXSYNC_CFG_1 => (x"00"), 00341 RCV_TERM_GND_1 => (TRUE), 00342 RCV_TERM_VTTRX_1 => (FALSE), 00343 RXEQ_CFG_1 => ("01111011"), 00344 TERMINATION_CTRL_1 => ("10100"), 00345 TERMINATION_OVRD_1 => (FALSE), 00346 TX_DETECT_RX_CFG_1 => (x"1832"), 00347 00348 --PRBS Detection Attributes 00349 RXPRBSERR_LOOPBACK_0 => ('0'), 00350 RXPRBSERR_LOOPBACK_1 => ('0'), 00351 00352 --Comma Detection and Alignment Attributes 00353 ALIGN_COMMA_WORD_0 => (1), 00354 COMMA_10B_ENABLE_0 => ("1111111111"), 00355 DEC_MCOMMA_DETECT_0 => (TRUE), 00356 DEC_PCOMMA_DETECT_0 => (TRUE), 00357 DEC_VALID_COMMA_ONLY_0 => (TRUE), 00358 MCOMMA_10B_VALUE_0 => ("1010000011"), 00359 MCOMMA_DETECT_0 => (TRUE), 00360 PCOMMA_10B_VALUE_0 => ("0101111100"), 00361 PCOMMA_DETECT_0 => (TRUE), 00362 RX_SLIDE_MODE_0 => ("PCS"), 00363 ALIGN_COMMA_WORD_1 => (1), 00364 COMMA_10B_ENABLE_1 => ("1111111111"), 00365 DEC_MCOMMA_DETECT_1 => (TRUE), 00366 DEC_PCOMMA_DETECT_1 => (TRUE), 00367 DEC_VALID_COMMA_ONLY_1 => (TRUE), 00368 MCOMMA_10B_VALUE_1 => ("1010000011"), 00369 MCOMMA_DETECT_1 => (TRUE), 00370 PCOMMA_10B_VALUE_1 => ("0101111100"), 00371 PCOMMA_DETECT_1 => (TRUE), 00372 RX_SLIDE_MODE_1 => ("PCS"), 00373 00374 --RX Loss-of-sync State Machine Attributes 00375 RX_LOS_INVALID_INCR_0 => (8), 00376 RX_LOS_THRESHOLD_0 => (128), 00377 RX_LOSS_OF_SYNC_FSM_0 => (FALSE), 00378 RX_LOS_INVALID_INCR_1 => (8), 00379 RX_LOS_THRESHOLD_1 => (128), 00380 RX_LOSS_OF_SYNC_FSM_1 => (FALSE), 00381 00382 --RX Elastic Buffer and Phase alignment Attributes 00383 RX_BUFFER_USE_0 => (TRUE), 00384 RX_EN_IDLE_RESET_BUF_0 => (TRUE), 00385 RX_IDLE_HI_CNT_0 => ("1000"), 00386 RX_IDLE_LO_CNT_0 => ("0000"), 00387 RX_XCLK_SEL_0 => ("RXREC"), 00388 RX_BUFFER_USE_1 => (TRUE), 00389 RX_EN_IDLE_RESET_BUF_1 => (TRUE), 00390 RX_IDLE_HI_CNT_1 => ("1000"), 00391 RX_IDLE_LO_CNT_1 => ("0000"), 00392 RX_XCLK_SEL_1 => ("RXREC"), 00393 00394 --Clock Correction Attributes 00395 CLK_COR_ADJ_LEN_0 => (1), 00396 CLK_COR_DET_LEN_0 => (1), 00397 CLK_COR_INSERT_IDLE_FLAG_0 => (FALSE), 00398 CLK_COR_KEEP_IDLE_0 => (FALSE), 00399 CLK_COR_MAX_LAT_0 => (20), 00400 CLK_COR_MIN_LAT_0 => (18), 00401 CLK_COR_PRECEDENCE_0 => (TRUE), 00402 CLK_COR_REPEAT_WAIT_0 => (0), 00403 CLK_COR_SEQ_1_1_0 => ("0100011100"), 00404 CLK_COR_SEQ_1_2_0 => ("0000000000"), 00405 CLK_COR_SEQ_1_3_0 => ("0000000000"), 00406 CLK_COR_SEQ_1_4_0 => ("0000000000"), 00407 CLK_COR_SEQ_1_ENABLE_0 => ("0001"), 00408 CLK_COR_SEQ_2_1_0 => ("0000000000"), 00409 CLK_COR_SEQ_2_2_0 => ("0000000000"), 00410 CLK_COR_SEQ_2_3_0 => ("0000000000"), 00411 CLK_COR_SEQ_2_4_0 => ("0000000000"), 00412 CLK_COR_SEQ_2_ENABLE_0 => ("0000"), 00413 CLK_COR_SEQ_2_USE_0 => (FALSE), 00414 CLK_CORRECT_USE_0 => (TRUE), 00415 RX_DECODE_SEQ_MATCH_0 => (TRUE), 00416 CLK_COR_ADJ_LEN_1 => (1), 00417 CLK_COR_DET_LEN_1 => (1), 00418 CLK_COR_INSERT_IDLE_FLAG_1 => (FALSE), 00419 CLK_COR_KEEP_IDLE_1 => (FALSE), 00420 CLK_COR_MAX_LAT_1 => (20), 00421 CLK_COR_MIN_LAT_1 => (18), 00422 CLK_COR_PRECEDENCE_1 => (TRUE), 00423 CLK_COR_REPEAT_WAIT_1 => (0), 00424 CLK_COR_SEQ_1_1_1 => ("0100011100"), 00425 CLK_COR_SEQ_1_2_1 => ("0000000000"), 00426 CLK_COR_SEQ_1_3_1 => ("0000000000"), 00427 CLK_COR_SEQ_1_4_1 => ("0000000000"), 00428 CLK_COR_SEQ_1_ENABLE_1 => ("0001"), 00429 CLK_COR_SEQ_2_1_1 => ("0000000000"), 00430 CLK_COR_SEQ_2_2_1 => ("0000000000"), 00431 CLK_COR_SEQ_2_3_1 => ("0000000000"), 00432 CLK_COR_SEQ_2_4_1 => ("0000000000"), 00433 CLK_COR_SEQ_2_ENABLE_1 => ("0000"), 00434 CLK_COR_SEQ_2_USE_1 => (FALSE), 00435 CLK_CORRECT_USE_1 => (TRUE), 00436 RX_DECODE_SEQ_MATCH_1 => (TRUE), 00437 00438 --Channel Bonding Attributes 00439 CHAN_BOND_1_MAX_SKEW_0 => (1), 00440 CHAN_BOND_2_MAX_SKEW_0 => (1), 00441 CHAN_BOND_KEEP_ALIGN_0 => (FALSE), 00442 CHAN_BOND_SEQ_1_1_0 => ("0001001010"), 00443 CHAN_BOND_SEQ_1_2_0 => ("0001001010"), 00444 CHAN_BOND_SEQ_1_3_0 => ("0001001010"), 00445 CHAN_BOND_SEQ_1_4_0 => ("0110111100"), 00446 CHAN_BOND_SEQ_1_ENABLE_0 => ("0000"), 00447 CHAN_BOND_SEQ_2_1_0 => ("0100111100"), 00448 CHAN_BOND_SEQ_2_2_0 => ("0100111100"), 00449 CHAN_BOND_SEQ_2_3_0 => ("0110111100"), 00450 CHAN_BOND_SEQ_2_4_0 => ("0100011100"), 00451 CHAN_BOND_SEQ_2_ENABLE_0 => ("0000"), 00452 CHAN_BOND_SEQ_2_USE_0 => (FALSE), 00453 CHAN_BOND_SEQ_LEN_0 => (1), 00454 RX_EN_MODE_RESET_BUF_0 => (TRUE), 00455 CHAN_BOND_1_MAX_SKEW_1 => (1), 00456 CHAN_BOND_2_MAX_SKEW_1 => (1), 00457 CHAN_BOND_KEEP_ALIGN_1 => (FALSE), 00458 CHAN_BOND_SEQ_1_1_1 => ("0001001010"), 00459 CHAN_BOND_SEQ_1_2_1 => ("0001001010"), 00460 CHAN_BOND_SEQ_1_3_1 => ("0001001010"), 00461 CHAN_BOND_SEQ_1_4_1 => ("0110111100"), 00462 CHAN_BOND_SEQ_1_ENABLE_1 => ("0000"), 00463 CHAN_BOND_SEQ_2_1_1 => ("0100111100"), 00464 CHAN_BOND_SEQ_2_2_1 => ("0100111100"), 00465 CHAN_BOND_SEQ_2_3_1 => ("0110111100"), 00466 CHAN_BOND_SEQ_2_4_1 => ("0100011100"), 00467 CHAN_BOND_SEQ_2_ENABLE_1 => ("0000"), 00468 CHAN_BOND_SEQ_2_USE_1 => (FALSE), 00469 CHAN_BOND_SEQ_LEN_1 => (1), 00470 RX_EN_MODE_RESET_BUF_1 => (TRUE), 00471 00472 --RX PCI Express Attributes 00473 CB2_INH_CC_PERIOD_0 => (8), 00474 CDR_PH_ADJ_TIME_0 => ("01010"), 00475 PCI_EXPRESS_MODE_0 => (TRUE), 00476 RX_EN_IDLE_HOLD_CDR_0 => (TRUE), 00477 RX_EN_IDLE_RESET_FR_0 => (TRUE), 00478 RX_EN_IDLE_RESET_PH_0 => (TRUE), 00479 RX_STATUS_FMT_0 => ("PCIE"), 00480 TRANS_TIME_FROM_P2_0 => (x"03c"), 00481 TRANS_TIME_NON_P2_0 => (x"19"), 00482 TRANS_TIME_TO_P2_0 => (x"064"), 00483 CB2_INH_CC_PERIOD_1 => (8), 00484 CDR_PH_ADJ_TIME_1 => ("01010"), 00485 PCI_EXPRESS_MODE_1 => (TRUE), 00486 RX_EN_IDLE_HOLD_CDR_1 => (TRUE), 00487 RX_EN_IDLE_RESET_FR_1 => (TRUE), 00488 RX_EN_IDLE_RESET_PH_1 => (TRUE), 00489 RX_STATUS_FMT_1 => ("PCIE"), 00490 TRANS_TIME_FROM_P2_1 => (x"03c"), 00491 TRANS_TIME_NON_P2_1 => (x"19"), 00492 TRANS_TIME_TO_P2_1 => (x"064"), 00493 00494 --RX SATA Attributes 00495 SATA_BURST_VAL_0 => ("100"), 00496 SATA_IDLE_VAL_0 => ("100"), 00497 SATA_MAX_BURST_0 => (7), 00498 SATA_MAX_INIT_0 => (22), 00499 SATA_MAX_WAKE_0 => (7), 00500 SATA_MIN_BURST_0 => (4), 00501 SATA_MIN_INIT_0 => (12), 00502 SATA_MIN_WAKE_0 => (4), 00503 SATA_BURST_VAL_1 => ("100"), 00504 SATA_IDLE_VAL_1 => ("100"), 00505 SATA_MAX_BURST_1 => (7), 00506 SATA_MAX_INIT_1 => (22), 00507 SATA_MAX_WAKE_1 => (7), 00508 SATA_MIN_BURST_1 => (4), 00509 SATA_MIN_INIT_1 => (12), 00510 SATA_MIN_WAKE_1 => (4) 00511 00512 00513 ) 00514 port map 00515 ( 00516 ------------------------ Loopback and Powerdown Ports ---------------------- 00517 LOOPBACK0 => tied_to_ground_vec_i(2 downto 0), 00518 LOOPBACK1 => tied_to_ground_vec_i(2 downto 0), 00519 RXPOWERDOWN0 => RXPOWERDOWN0_IN, 00520 RXPOWERDOWN1 => RXPOWERDOWN1_IN, 00521 TXPOWERDOWN0 => TXPOWERDOWN0_IN, 00522 TXPOWERDOWN1 => TXPOWERDOWN1_IN, 00523 --------------------------------- PLL Ports -------------------------------- 00524 CLK00 => CLK00_IN, 00525 CLK01 => CLK01_IN, 00526 CLK10 => tied_to_ground_i, 00527 CLK11 => tied_to_ground_i, 00528 CLKINEAST0 => tied_to_ground_i, 00529 CLKINEAST1 => tied_to_ground_i, 00530 CLKINWEST0 => tied_to_ground_i, 00531 CLKINWEST1 => tied_to_ground_i, 00532 GCLK00 => tied_to_ground_i, 00533 GCLK01 => tied_to_ground_i, 00534 GCLK10 => tied_to_ground_i, 00535 GCLK11 => tied_to_ground_i, 00536 GTPRESET0 => GTPRESET0_IN, 00537 GTPRESET1 => GTPRESET1_IN, 00538 GTPTEST0 => "00010000", 00539 GTPTEST1 => "00010000", 00540 INTDATAWIDTH0 => tied_to_vcc_i, 00541 INTDATAWIDTH1 => tied_to_vcc_i, 00542 PLLCLK00 => tied_to_ground_i, 00543 PLLCLK01 => tied_to_ground_i, 00544 PLLCLK10 => tied_to_ground_i, 00545 PLLCLK11 => tied_to_ground_i, 00546 PLLLKDET0 => PLLLKDET0_OUT, 00547 PLLLKDET1 => PLLLKDET1_OUT, 00548 PLLLKDETEN0 => tied_to_vcc_i, 00549 PLLLKDETEN1 => tied_to_vcc_i, 00550 PLLPOWERDOWN0 => tied_to_ground_i, 00551 PLLPOWERDOWN1 => tied_to_ground_i, 00552 REFCLKOUT0 => open, 00553 REFCLKOUT1 => open, 00554 REFCLKPLL0 => open, 00555 REFCLKPLL1 => open, 00556 REFCLKPWRDNB0 => tied_to_vcc_i, 00557 REFCLKPWRDNB1 => tied_to_vcc_i, 00558 REFSELDYPLL0 => tied_to_ground_vec_i(2 downto 0), 00559 REFSELDYPLL1 => tied_to_ground_vec_i(2 downto 0), 00560 RESETDONE0 => RESETDONE0_OUT, 00561 RESETDONE1 => RESETDONE1_OUT, 00562 TSTCLK0 => tied_to_ground_i, 00563 TSTCLK1 => tied_to_ground_i, 00564 TSTIN0 => tied_to_ground_vec_i(11 downto 0), 00565 TSTIN1 => tied_to_ground_vec_i(11 downto 0), 00566 TSTOUT0 => open, 00567 TSTOUT1 => open, 00568 ----------------------- Receive Ports - 8b10b Decoder ---------------------- 00569 RXCHARISCOMMA0 => open, 00570 RXCHARISCOMMA1 => open, 00571 RXCHARISK0(3 downto 2) => rxcharisk0_float_i , 00572 RXCHARISK0(1 downto 0) => RXCHARISK0_OUT, 00573 RXCHARISK1(3 downto 2) => rxcharisk1_float_i , 00574 RXCHARISK1(1 downto 0) => RXCHARISK1_OUT, 00575 RXDEC8B10BUSE0 => tied_to_vcc_i, 00576 RXDEC8B10BUSE1 => tied_to_vcc_i, 00577 RXDISPERR0(3 downto 2) => rxdisperr0_float_i , 00578 RXDISPERR0(1 downto 0) => RXDISPERR0_OUT, 00579 RXDISPERR1(3 downto 2) => rxdisperr1_float_i , 00580 RXDISPERR1(1 downto 0) => RXDISPERR1_OUT, 00581 RXNOTINTABLE0(3 downto 2) => rxnotintable0_float_i , 00582 RXNOTINTABLE0(1 downto 0) => RXNOTINTABLE0_OUT, 00583 RXNOTINTABLE1(3 downto 2) => rxnotintable1_float_i , 00584 RXNOTINTABLE1(1 downto 0) => RXNOTINTABLE1_OUT, 00585 RXRUNDISP0 => open, 00586 RXRUNDISP1 => open, 00587 USRCODEERR0 => tied_to_ground_i, 00588 USRCODEERR1 => tied_to_ground_i, 00589 ---------------------- Receive Ports - Channel Bonding --------------------- 00590 RXCHANBONDSEQ0 => open, 00591 RXCHANBONDSEQ1 => open, 00592 RXCHANISALIGNED0 => open, 00593 RXCHANISALIGNED1 => open, 00594 RXCHANREALIGN0 => open, 00595 RXCHANREALIGN1 => open, 00596 RXCHBONDI => tied_to_ground_vec_i(2 downto 0), 00597 RXCHBONDMASTER0 => tied_to_ground_i, 00598 RXCHBONDMASTER1 => tied_to_ground_i, 00599 RXCHBONDO => open, 00600 RXCHBONDSLAVE0 => tied_to_ground_i, 00601 RXCHBONDSLAVE1 => tied_to_ground_i, 00602 RXENCHANSYNC0 => tied_to_ground_i, 00603 RXENCHANSYNC1 => tied_to_ground_i, 00604 ---------------------- Receive Ports - Clock Correction -------------------- 00605 RXCLKCORCNT0 => RXCLKCORCNT0_OUT, 00606 RXCLKCORCNT1 => RXCLKCORCNT1_OUT, 00607 --------------- Receive Ports - Comma Detection and Alignment -------------- 00608 RXBYTEISALIGNED0 => open, 00609 RXBYTEISALIGNED1 => open, 00610 RXBYTEREALIGN0 => open, 00611 RXBYTEREALIGN1 => open, 00612 RXCOMMADET0 => open, 00613 RXCOMMADET1 => open, 00614 RXCOMMADETUSE0 => tied_to_vcc_i, 00615 RXCOMMADETUSE1 => tied_to_vcc_i, 00616 RXENMCOMMAALIGN0 => RXENMCOMMAALIGN0_IN, 00617 RXENMCOMMAALIGN1 => RXENMCOMMAALIGN1_IN, 00618 RXENPCOMMAALIGN0 => RXENPCOMMAALIGN0_IN, 00619 RXENPCOMMAALIGN1 => RXENPCOMMAALIGN1_IN, 00620 RXSLIDE0 => tied_to_ground_i, 00621 RXSLIDE1 => tied_to_ground_i, 00622 ----------------------- Receive Ports - PRBS Detection --------------------- 00623 PRBSCNTRESET0 => tied_to_ground_i, 00624 PRBSCNTRESET1 => tied_to_ground_i, 00625 RXENPRBSTST0 => tied_to_ground_vec_i(2 downto 0), 00626 RXENPRBSTST1 => tied_to_ground_vec_i(2 downto 0), 00627 RXPRBSERR0 => open, 00628 RXPRBSERR1 => open, 00629 ------------------- Receive Ports - RX Data Path interface ----------------- 00630 RXDATA0 => rxdata0_i, 00631 RXDATA1 => rxdata1_i, 00632 RXDATAWIDTH0 => "01", 00633 RXDATAWIDTH1 => "01", 00634 RXRECCLK0 => open, 00635 RXRECCLK1 => open, 00636 RXRESET0 => RXRESET0_IN, 00637 RXRESET1 => RXRESET1_IN, 00638 RXUSRCLK0 => RXUSRCLK0_IN, 00639 RXUSRCLK1 => RXUSRCLK1_IN, 00640 RXUSRCLK20 => RXUSRCLK20_IN, 00641 RXUSRCLK21 => RXUSRCLK21_IN, 00642 ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ 00643 GATERXELECIDLE0 => GATERXELECIDLE0_IN, 00644 GATERXELECIDLE1 => GATERXELECIDLE1_IN, 00645 IGNORESIGDET0 => IGNORESIGDET0_IN, 00646 IGNORESIGDET1 => IGNORESIGDET1_IN, 00647 RCALINEAST => tied_to_ground_vec_i(4 downto 0), 00648 RCALINWEST => tied_to_ground_vec_i(4 downto 0), 00649 RCALOUTEAST => open, 00650 RCALOUTWEST => open, 00651 RXCDRRESET0 => tied_to_ground_i, 00652 RXCDRRESET1 => tied_to_ground_i, 00653 RXELECIDLE0 => RXELECIDLE0_OUT, 00654 RXELECIDLE1 => RXELECIDLE1_OUT, 00655 RXEQMIX0 => "11", 00656 RXEQMIX1 => "11", 00657 RXN0 => RXN0_IN, 00658 RXN1 => RXN1_IN, 00659 RXP0 => RXP0_IN, 00660 RXP1 => RXP1_IN, 00661 ----------- Receive Ports - RX Elastic Buffer and Phase Alignment ---------- 00662 RXBUFRESET0 => tied_to_ground_i, 00663 RXBUFRESET1 => tied_to_ground_i, 00664 RXBUFSTATUS0 => open, 00665 RXBUFSTATUS1 => open, 00666 RXENPMAPHASEALIGN0 => tied_to_ground_i, 00667 RXENPMAPHASEALIGN1 => tied_to_ground_i, 00668 RXPMASETPHASE0 => tied_to_ground_i, 00669 RXPMASETPHASE1 => tied_to_ground_i, 00670 RXSTATUS0 => RXSTATUS0_OUT, 00671 RXSTATUS1 => RXSTATUS1_OUT, 00672 --------------- Receive Ports - RX Loss-of-sync State Machine -------------- 00673 RXLOSSOFSYNC0 => open, 00674 RXLOSSOFSYNC1 => open, 00675 -------------- Receive Ports - RX Pipe Control for PCI Express ------------- 00676 PHYSTATUS0 => PHYSTATUS0_OUT, 00677 PHYSTATUS1 => PHYSTATUS1_OUT, 00678 RXVALID0 => RXVALID0_OUT, 00679 RXVALID1 => RXVALID1_OUT, 00680 -------------------- Receive Ports - RX Polarity Control ------------------- 00681 RXPOLARITY0 => RXPOLARITY0_IN, 00682 RXPOLARITY1 => RXPOLARITY1_IN, 00683 ------------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------ 00684 DADDR => tied_to_ground_vec_i(7 downto 0), 00685 DCLK => tied_to_ground_i, 00686 DEN => tied_to_ground_i, 00687 DI => tied_to_ground_vec_i(15 downto 0), 00688 DRDY => open, 00689 DRPDO => open, 00690 DWE => tied_to_ground_i, 00691 ---------------------------- TX/RX Datapath Ports -------------------------- 00692 GTPCLKFBEAST => open, 00693 GTPCLKFBSEL0EAST => "10", 00694 GTPCLKFBSEL0WEST => "00", 00695 GTPCLKFBSEL1EAST => "11", 00696 GTPCLKFBSEL1WEST => "01", 00697 GTPCLKFBWEST => open, 00698 GTPCLKOUT0 => GTPCLKOUT0_OUT, 00699 GTPCLKOUT1 => GTPCLKOUT1_OUT, 00700 ------------------- Transmit Ports - 8b10b Encoder Control ----------------- 00701 TXBYPASS8B10B0 => tied_to_ground_vec_i(3 downto 0), 00702 TXBYPASS8B10B1 => tied_to_ground_vec_i(3 downto 0), 00703 TXCHARDISPMODE0(3 downto 2) => tied_to_ground_vec_i(1 downto 0), 00704 TXCHARDISPMODE0(1 downto 0) => TXCHARDISPMODE0_IN, 00705 TXCHARDISPMODE1(3 downto 2) => tied_to_ground_vec_i(1 downto 0), 00706 TXCHARDISPMODE1(1 downto 0) => TXCHARDISPMODE1_IN, 00707 TXCHARDISPVAL0 => tied_to_ground_vec_i(3 downto 0), 00708 TXCHARDISPVAL1 => tied_to_ground_vec_i(3 downto 0), 00709 TXCHARISK0(3 downto 2) => tied_to_ground_vec_i (1 downto 0), 00710 TXCHARISK0(1 downto 0) => TXCHARISK0_IN, 00711 TXCHARISK1(3 downto 2) => tied_to_ground_vec_i (1 downto 0), 00712 TXCHARISK1(1 downto 0) => TXCHARISK1_IN, 00713 TXENC8B10BUSE0 => tied_to_vcc_i, 00714 TXENC8B10BUSE1 => tied_to_vcc_i, 00715 TXKERR0 => open, 00716 TXKERR1 => open, 00717 TXRUNDISP0 => open, 00718 TXRUNDISP1 => open, 00719 --------------- Transmit Ports - TX Buffer and Phase Alignment ------------- 00720 TXBUFSTATUS0 => open, 00721 TXBUFSTATUS1 => open, 00722 TXENPMAPHASEALIGN0 => tied_to_ground_i, 00723 TXENPMAPHASEALIGN1 => tied_to_ground_i, 00724 TXPMASETPHASE0 => tied_to_ground_i, 00725 TXPMASETPHASE1 => tied_to_ground_i, 00726 ------------------ Transmit Ports - TX Data Path interface ----------------- 00727 TXDATA0 => txdata0_i, 00728 TXDATA1 => txdata1_i, 00729 TXDATAWIDTH0 => "01", 00730 TXDATAWIDTH1 => "01", 00731 TXOUTCLK0 => open, 00732 TXOUTCLK1 => open, 00733 TXRESET0 => tied_to_ground_i, 00734 TXRESET1 => tied_to_ground_i, 00735 TXUSRCLK0 => TXUSRCLK0_IN, 00736 TXUSRCLK1 => TXUSRCLK1_IN, 00737 TXUSRCLK20 => TXUSRCLK20_IN, 00738 TXUSRCLK21 => TXUSRCLK21_IN, 00739 --------------- Transmit Ports - TX Driver and OOB signalling -------------- 00740 TXBUFDIFFCTRL0 => "101", 00741 TXBUFDIFFCTRL1 => "101", 00742 TXDIFFCTRL0 => "1001", 00743 TXDIFFCTRL1 => "1001", 00744 TXINHIBIT0 => tied_to_ground_i, 00745 TXINHIBIT1 => tied_to_ground_i, 00746 TXN0 => TXN0_OUT, 00747 TXN1 => TXN1_OUT, 00748 TXP0 => TXP0_OUT, 00749 TXP1 => TXP1_OUT, 00750 TXPREEMPHASIS0 => "000", 00751 TXPREEMPHASIS1 => "000", 00752 --------------------- Transmit Ports - TX PRBS Generator ------------------- 00753 TXENPRBSTST0 => tied_to_ground_vec_i(2 downto 0), 00754 TXENPRBSTST1 => tied_to_ground_vec_i(2 downto 0), 00755 TXPRBSFORCEERR0 => tied_to_ground_i, 00756 TXPRBSFORCEERR1 => tied_to_ground_i, 00757 -------------------- Transmit Ports - TX Polarity Control ------------------ 00758 TXPOLARITY0 => tied_to_ground_i, 00759 TXPOLARITY1 => tied_to_ground_i, 00760 ----------------- Transmit Ports - TX Ports for PCI Express ---------------- 00761 TXDETECTRX0 => TXDETECTRX0_IN, 00762 TXDETECTRX1 => TXDETECTRX1_IN, 00763 TXELECIDLE0 => TXELECIDLE0_IN, 00764 TXELECIDLE1 => TXELECIDLE1_IN, 00765 TXPDOWNASYNCH0 => tied_to_ground_i, 00766 TXPDOWNASYNCH1 => tied_to_ground_i, 00767 --------------------- Transmit Ports - TX Ports for SATA ------------------- 00768 TXCOMSTART0 => tied_to_ground_i, 00769 TXCOMSTART1 => tied_to_ground_i, 00770 TXCOMTYPE0 => tied_to_ground_i, 00771 TXCOMTYPE1 => tied_to_ground_i 00772 00773 ); 00774 00775 end RTL; 00776 00777
1.7.4