pcie_src/pcie_core64_m1/source_virtex6/gtx_drp_chanalign_fix_3752_v6.vhd

-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
-- Project    : Virtex-6 Integrated Block for PCI Express
-- File       : gtx_drp_chanalign_fix_3752_v6.vhd
-- Version    : 2.3
---- Description: Virtex6 Workaround for deadlock due lane-lane skew Bug
----
----
----
----------------------------------------------------------------------------------

library ieee;
   use ieee.std_logic_1164.all;
   use ieee.std_logic_unsigned.all;

entity GTX_DRP_CHANALIGN_FIX_3752_V6 is
   generic (
      C_SIMULATION                              : integer := 0    -- Set to 1 for simulation

   );
   port (
      dwe                                       : out std_logic;
      din                                       : out std_logic_vector(15 downto 0);      --THIS IS THE INPUT TO THE DRP
      den                                       : out std_logic;
      daddr                                     : out std_logic_vector(7 downto 0);
      drpstate                                  : out std_logic_vector(3 downto 0);      --DEBUG
      write_ts1                                 : in std_logic;
      write_fts                                 : in std_logic;
      dout                                      : in std_logic_vector(15 downto 0);      --THIS IS THE OUTPUT OF THE DRP
      drdy                                      : in std_logic;
      Reset_n                                   : in std_logic;
      drp_clk                                   : in std_logic
   );
end GTX_DRP_CHANALIGN_FIX_3752_V6;

architecture v6_pcie of GTX_DRP_CHANALIGN_FIX_3752_V6 is

   constant TCQ                      : integer := 1;
   constant DRP_IDLE_FTS             : std_logic_vector(3 downto 0) := "0001";
   constant DRP_IDLE_TS1             : std_logic_vector(3 downto 0) := "0010";
   constant DRP_RESET                : std_logic_vector(3 downto 0) := "0011";
   constant DRP_WRITE_FTS            : std_logic_vector(3 downto 0) := "0110";
   constant DRP_WRITE_DONE_FTS       : std_logic_vector(3 downto 0) := "0111";
   constant DRP_WRITE_TS1            : std_logic_vector(3 downto 0) := "1000";
   constant DRP_WRITE_DONE_TS1       : std_logic_vector(3 downto 0) := "1001";
   constant DRP_COM                  : std_logic_vector(9 downto 0) := "0110111100";
   constant DRP_FTS                  : std_logic_vector(9 downto 0) := "0100111100";
   constant DRP_TS1                  : std_logic_vector(9 downto 0) := "0001001010";

   signal next_daddr                              : std_logic_vector(7 downto 0);
   signal next_drpstate                           : std_logic_vector(3 downto 0);
   signal write_ts1_gated                         : std_logic;
   signal write_fts_gated                         : std_logic;

   -- Declare intermediate signals for referenced outputs
   signal daddr_v6pcie                           : std_logic_vector(7 downto 0);
   signal drpstate_v6pcie                        : std_logic_vector(3 downto 0);

begin
   -- Drive referenced outputs
   daddr <= daddr_v6pcie;
   drpstate <= drpstate_v6pcie;

   process (drp_clk)
   begin
      if (drp_clk'event and drp_clk = '1') then

         if ((not(Reset_n)) = '1') then

            daddr_v6pcie <= X"08" after (TCQ)*1 ps;
            drpstate_v6pcie <= DRP_RESET after (TCQ)*1 ps;

            write_ts1_gated <= '0' after (TCQ)*1 ps;
            write_fts_gated <= '0' after (TCQ)*1 ps;

         else

            daddr_v6pcie <= next_daddr after (TCQ)*1 ps;
            drpstate_v6pcie <= next_drpstate after (TCQ)*1 ps;

            write_ts1_gated <= write_ts1 after (TCQ)*1 ps;
            write_fts_gated <= write_fts after (TCQ)*1 ps;

         end if;

      end if;

   end process;


   process (drpstate_v6pcie, daddr_v6pcie, drdy, write_ts1_gated, write_fts_gated)
   begin

      -- DEFAULT CONDITIONS
      next_drpstate <= drpstate_v6pcie;
      next_daddr <= daddr_v6pcie;
      den <= '0';
      din <= (others => '0');
      dwe <= '0';

      case drpstate_v6pcie is

         -- RESET CONDITION, WE NEED TO READ THE TOP 6 BITS OF THE DRP REGISTER WHEN WE GET THE WRITE FTS TRIGGER
         when DRP_RESET =>
            next_drpstate <= DRP_WRITE_TS1;
            next_daddr <= X"08";

         -- WRITE FTS SEQUENCE
         when DRP_WRITE_FTS =>
            den <= '1';
            dwe <= '1';
            if (daddr_v6pcie = X"08") then
               din <= X"FD3C";
            elsif (daddr_v6pcie = X"09") then
               din <= X"C53C";
            elsif (daddr_v6pcie = X"0A") then
               din <= X"FDBC";
            elsif (daddr_v6pcie = X"0B") then
               din <= X"853C";
            end if;
            next_drpstate <= DRP_WRITE_DONE_FTS;

         -- WAIT FOR FTS SEQUENCE WRITE TO FINISH, ONCE WE FINISH ALL WRITES GO TO FTS IDLE
         when DRP_WRITE_DONE_FTS =>
            if (drdy = '1') then
               if (daddr_v6pcie = X"0B") then
                  next_drpstate <= DRP_IDLE_FTS;
                  next_daddr <= X"08";
               else
                  next_drpstate <= DRP_WRITE_FTS;
                  next_daddr <= daddr_v6pcie + X"01";
               end if;
            end if;

         -- FTS IDLE: WAIT HERE UNTIL WE NEED TO WRITE TS1
         when DRP_IDLE_FTS =>
            if (write_ts1_gated = '1') then
               next_drpstate <= DRP_WRITE_TS1;
               next_daddr <= X"08";
            end if;

         -- WRITE TS1 SEQUENCE
         when DRP_WRITE_TS1 =>
            den <= '1';
            dwe <= '1';
            if (daddr_v6pcie = X"08") then
               din <= X"FC4A";
            elsif (daddr_v6pcie = X"09") then
               din <= X"DC4A";
            elsif (daddr_v6pcie = X"0A") then
               din <= X"C04A";
            elsif (daddr_v6pcie = X"0B") then
               din <= X"85BC";
            end if;
            next_drpstate <= DRP_WRITE_DONE_TS1;

         -- WAIT FOR TS1 SEQUENCE WRITE TO FINISH, ONCE WE FINISH ALL WRITES GO TO TS1 IDLE
         when DRP_WRITE_DONE_TS1 =>
            if (drdy = '1') then
               if (daddr_v6pcie = X"0B") then
                  next_drpstate <= DRP_IDLE_TS1;
                  next_daddr <= X"08";
               else
                  next_drpstate <= DRP_WRITE_TS1;
                  next_daddr <= daddr_v6pcie + X"01";
               end if;
            end if;

         -- TS1 IDLE: WAIT HERE UNTIL WE NEED TO WRITE FTS
         when DRP_IDLE_TS1 =>
            if (write_fts_gated = '1') then
               next_drpstate <= DRP_WRITE_FTS;
               next_daddr <= X"08";
            end if;
        when others =>
               next_drpstate <= DRP_RESET;
               next_daddr <= X"00";
      end case;
   end process;


end v6_pcie;