Граф наследования:GTX_DRP_CHANALIGN_FIX_3752_V6:
Architectures | |
| v6_pcie | Architecture |
Libraries | |
| ieee | |
Packages | |
| std_logic_1164 | |
| std_logic_unsigned | |
Generics | |
| C_SIMULATION | integer := 0 |
Ports | |
| dwe | out std_logic |
| din | out std_logic_vector ( 15 downto 0 ) |
| den | out std_logic |
| daddr | out std_logic_vector ( 7 downto 0 ) |
| drpstate | out std_logic_vector ( 3 downto 0 ) |
| write_ts1 | in std_logic |
| write_fts | in std_logic |
| dout | in std_logic_vector ( 15 downto 0 ) |
| drdy | in std_logic |
| Reset_n | in std_logic |
| drp_clk | in std_logic |
Подробное описание
См. определение в файле gtx_drp_chanalign_fix_3752_v6.vhd строка 64
Объявления и описания членов класса находятся в файле:
- pcie_src/pcie_core64_m1/source_virtex6/gtx_drp_chanalign_fix_3752_v6.vhd
