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DS_DMA
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00001 00002 ------------------------------------------------------------------------------- 00003 -- 00004 -- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved. 00005 -- 00006 -- This file contains confidential and proprietary information 00007 -- of Xilinx, Inc. and is protected under U.S. and 00008 -- international copyright and other intellectual property 00009 -- laws. 00010 -- 00011 -- DISCLAIMER 00012 -- This disclaimer is not a license and does not grant any 00013 -- rights to the materials distributed herewith. Except as 00014 -- otherwise provided in a valid license issued to you by 00015 -- Xilinx, and to the maximum extent permitted by applicable 00016 -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 00017 -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 00018 -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 00019 -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 00020 -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 00021 -- (2) Xilinx shall not be liable (whether in contract or tort, 00022 -- including negligence, or under any other theory of 00023 -- liability) for any loss or damage of any kind or nature 00024 -- related to, arising under or in connection with these 00025 -- materials, including for any direct, or any indirect, 00026 -- special, incidental, or consequential loss or damage 00027 -- (including loss of data, profits, goodwill, or any type of 00028 -- loss or damage suffered as a result of any action brought 00029 -- by a third party) even if such damage or loss was 00030 -- reasonably foreseeable or Xilinx had been advised of the 00031 -- possibility of the same. 00032 -- 00033 -- CRITICAL APPLICATIONS 00034 -- Xilinx products are not designed or intended to be fail- 00035 -- safe, or for use in any application requiring fail-safe 00036 -- performance, such as life-support or safety devices or 00037 -- systems, Class III medical devices, nuclear facilities, 00038 -- applications related to the deployment of airbags, or any 00039 -- other applications that could lead to death, personal 00040 -- injury, or severe property or environmental damage 00041 -- (individually and collectively, "Critical 00042 -- Applications"). Customer assumes the sole risk and 00043 -- liability of any use of Xilinx products in Critical 00044 -- Applications, subject only to applicable laws and 00045 -- regulations governing limitations on product liability. 00046 -- 00047 -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 00048 -- PART OF THIS FILE AT ALL TIMES. 00049 -- 00050 ------------------------------------------------------------------------------- 00051 -- Project : Virtex-6 Integrated Block for PCI Express 00052 -- File : gtx_rx_valid_filter_v6.vhd 00053 -- Version : 2.3 00054 ------------------------------------------------------------------------------- 00055 library ieee; 00056 use ieee.std_logic_1164.all; 00057 use ieee.std_logic_unsigned.all; 00058 00059 library unisim; 00060 use unisim.vcomponents.all; 00061 00062 entity GTX_RX_VALID_FILTER_V6 is 00063 generic ( 00064 00065 CLK_COR_MIN_LAT : integer := 28 00066 ); 00067 port ( 00068 USER_RXCHARISK : out std_logic_vector(1 downto 0); 00069 USER_RXDATA : out std_logic_vector(15 downto 0); 00070 USER_RXVALID : out std_logic; 00071 USER_RXELECIDLE : out std_logic; 00072 USER_RX_STATUS : out std_logic_vector(2 downto 0); 00073 USER_RX_PHY_STATUS : out std_logic; 00074 GT_RXCHARISK : in std_logic_vector(1 downto 0); 00075 GT_RXDATA : in std_logic_vector(15 downto 0); 00076 GT_RXVALID : in std_logic; 00077 GT_RXELECIDLE : in std_logic; 00078 GT_RX_STATUS : in std_logic_vector(2 downto 0); 00079 GT_RX_PHY_STATUS : in std_logic; 00080 PLM_IN_L0 : in std_logic; 00081 PLM_IN_RS : in std_logic; 00082 USER_CLK : in std_logic; 00083 RESET : in std_logic 00084 ); 00085 end GTX_RX_VALID_FILTER_V6; 00086 00087 architecture v6_pcie of GTX_RX_VALID_FILTER_V6 is 00088 00089 constant TCQ : integer := 1; 00090 00091 constant EIOS_DET_IDL : std_logic_vector(4 downto 0) := "00001"; 00092 constant EIOS_DET_NO_STR0 : std_logic_vector(4 downto 0) := "00010"; 00093 constant EIOS_DET_STR0 : std_logic_vector(4 downto 0) := "00100"; 00094 constant EIOS_DET_STR1 : std_logic_vector(4 downto 0) := "01000"; 00095 constant EIOS_DET_DONE : std_logic_vector(4 downto 0) := "10000"; 00096 00097 constant EIOS_COM : std_logic_vector(7 downto 0) := "10111100"; 00098 constant EIOS_IDL : std_logic_vector(7 downto 0) := "01111100"; 00099 constant FTSOS_COM : std_logic_vector(7 downto 0) := "10111100"; 00100 constant FTSOS_FTS : std_logic_vector(7 downto 0) := "00111100"; 00101 00102 constant USER_RXVLD_IDL : std_logic_vector(3 downto 0) := "0001"; 00103 constant USER_RXVLD_EI : std_logic_vector(3 downto 0) := "0010"; 00104 constant USER_RXVLD_EI_DB0 : std_logic_vector(3 downto 0) := "0100"; 00105 constant USER_RXVLD_EI_DB1 : std_logic_vector(3 downto 0) := "1000"; 00106 00107 constant TS1_FILTER_IDLE : std_logic_vector(2 downto 0) := "001"; 00108 constant TS1_FILTER_WAITVALID : std_logic_vector(2 downto 0) := "010"; 00109 constant TS1_FILTER_DB : std_logic_vector(2 downto 0) := "100"; 00110 00111 FUNCTION to_stdlogicvector ( 00112 val_in : IN integer; 00113 length : IN integer) RETURN std_logic_vector IS 00114 00115 VARIABLE ret : std_logic_vector(length-1 DOWNTO 0) := (OTHERS => '0'); 00116 VARIABLE num : integer := val_in; 00117 VARIABLE x : integer; 00118 BEGIN 00119 FOR index IN 0 TO length-1 LOOP 00120 x := num rem 2; 00121 num := num/2; 00122 IF (x = 1) THEN 00123 ret(index) := '1'; 00124 ELSE 00125 ret(index) := '0'; 00126 END IF; 00127 END LOOP; 00128 RETURN(ret); 00129 END to_stdlogicvector; 00130 00131 FUNCTION to_stdlogic ( 00132 in_val : IN boolean) RETURN std_logic IS 00133 BEGIN 00134 IF (in_val) THEN 00135 RETURN('1'); 00136 ELSE 00137 RETURN('0'); 00138 END IF; 00139 END to_stdlogic; 00140 00141 signal reg_state_eios_det : std_logic_vector(4 downto 0); 00142 signal state_eios_det : std_logic_vector(4 downto 0); 00143 signal reg_eios_detected : std_logic; 00144 signal eios_detected : std_logic; 00145 signal reg_symbol_after_eios : std_logic; 00146 signal symbol_after_eios : std_logic; 00147 00148 signal reg_state_rxvld_ei : std_logic_vector(3 downto 0); 00149 signal state_rxvld_ei : std_logic_vector(3 downto 0); 00150 00151 signal reg_rxvld_count : std_logic_vector(4 downto 0); 00152 signal rxvld_count : std_logic_vector(4 downto 0); 00153 00154 signal reg_rxvld_fallback : std_logic_vector(3 downto 0); 00155 signal rxvld_fallback : std_logic_vector(3 downto 0); 00156 00157 signal gt_rxcharisk_q : std_logic_vector(1 downto 0); 00158 signal gt_rxdata_q : std_logic_vector(15 downto 0); 00159 signal gt_rxvalid_q : std_logic; 00160 signal gt_rxelecidle_q : std_logic; 00161 signal gt_rxelecidle_qq : std_logic; 00162 00163 signal gt_rx_status_q : std_logic_vector(2 downto 0); 00164 signal gt_rx_phy_status_q : std_logic; 00165 signal gt_rx_is_skp0_q : std_logic; 00166 signal gt_rx_is_skp1_q : std_logic; 00167 00168 signal ts1_state : std_logic_vector(2 downto 0); 00169 signal next_ts1_state : std_logic_vector(2 downto 0); 00170 signal ts1_resetcount : std_logic; 00171 signal ts1_count : std_logic_vector(8 downto 0); 00172 signal ts1_filter_done : std_logic; 00173 signal next_ts1_filter_done : std_logic; 00174 00175 signal awake_in_progress_q : std_logic := '0'; 00176 signal awake_in_progress : std_logic := '0'; 00177 signal awake_see_com_q : std_logic := '0'; 00178 signal awake_com_count_q : std_logic_vector(3 downto 0) := "0000"; 00179 signal awake_com_count : std_logic_vector(3 downto 0) := "0000"; 00180 signal awake_com_count_inced : std_logic_vector(3 downto 0) := "0000"; 00181 00182 signal awake_see_com_0 : std_logic; 00183 signal awake_see_com_1 : std_logic; 00184 signal awake_see_com : std_logic; 00185 signal awake_done : std_logic; 00186 signal awake_start : std_logic; 00187 00188 signal rst_l : std_logic; 00189 00190 00191 -- Declare intermediate signals for referenced outputs 00192 signal USER_RXVALID_v6pcie1 : std_logic; 00193 signal USER_RXELECIDLE_v6pcie0 : std_logic; 00194 00195 begin 00196 -- Drive referenced outputs 00197 USER_RXVALID <= USER_RXVALID_v6pcie1; 00198 USER_RXELECIDLE <= USER_RXELECIDLE_v6pcie0; 00199 00200 -- EIOS detector 00201 00202 process (USER_CLK) 00203 begin 00204 if (USER_CLK'event and USER_CLK = '1') then 00205 00206 if (RESET = '1') then 00207 00208 reg_eios_detected <= '0' after (TCQ)*1 ps; 00209 reg_state_eios_det <= EIOS_DET_IDL after (TCQ)*1 ps; 00210 reg_symbol_after_eios <= '0' after (TCQ)*1 ps; 00211 gt_rxcharisk_q <= "00" after (TCQ)*1 ps; 00212 gt_rxdata_q <= "0000000000000000" after (TCQ)*1 ps; 00213 gt_rxvalid_q <= '0' after (TCQ)*1 ps; 00214 gt_rxelecidle_q <= '0' after (TCQ)*1 ps; 00215 gt_rxelecidle_qq <= '0' after (TCQ)*1 ps; 00216 gt_rx_status_q <= "000" after (TCQ)*1 ps; 00217 00218 gt_rx_phy_status_q <= '0' after (TCQ)*1 ps; 00219 gt_rx_is_skp0_q <= '0' after (TCQ)*1 ps; 00220 gt_rx_is_skp1_q <= '0' after (TCQ)*1 ps; 00221 00222 else 00223 00224 reg_eios_detected <= '0' after (TCQ)*1 ps; 00225 reg_symbol_after_eios <= '0' after (TCQ)*1 ps; 00226 gt_rxcharisk_q <= GT_RXCHARISK after (TCQ)*1 ps; 00227 gt_rxdata_q <= GT_RXDATA after (TCQ)*1 ps; 00228 gt_rxvalid_q <= GT_RXVALID after (TCQ)*1 ps; 00229 gt_rxelecidle_q <= GT_RXELECIDLE after (TCQ)*1 ps; 00230 gt_rxelecidle_qq <= gt_rxelecidle_q after (TCQ)*1 ps; 00231 gt_rx_status_q <= GT_RX_STATUS after (TCQ)*1 ps; 00232 00233 gt_rx_phy_status_q <= GT_RX_PHY_STATUS after (TCQ)*1 ps; 00234 00235 if ((GT_RXCHARISK(0) = '1') and (GT_RXDATA(7 downto 0) = FTSOS_FTS)) then 00236 gt_rx_is_skp0_q <= '1' after (TCQ)*1 ps; 00237 else 00238 gt_rx_is_skp0_q <= '0' after (TCQ)*1 ps; 00239 end if; 00240 00241 if ((GT_RXCHARISK(1) = '1') and (GT_RXDATA(15 downto 8) = FTSOS_FTS)) then 00242 gt_rx_is_skp1_q <= '1' after (TCQ)*1 ps; 00243 else 00244 gt_rx_is_skp1_q <= '0' after (TCQ)*1 ps; 00245 end if; 00246 00247 case state_eios_det is 00248 00249 when EIOS_DET_IDL => 00250 if ((gt_rxcharisk_q(0) = '1') and (gt_rxdata_q(7 downto 0) = EIOS_COM) and (gt_rxcharisk_q(1) = '1') and (gt_rxdata_q(15 downto 8) = EIOS_IDL)) then 00251 reg_state_eios_det <= EIOS_DET_NO_STR0 after (TCQ)*1 ps; 00252 reg_eios_detected <= '1' after (TCQ)*1 ps; 00253 elsif ((gt_rxcharisk_q(1) = '1') and (gt_rxdata_q(15 downto 8) = EIOS_COM)) then 00254 reg_state_eios_det <= EIOS_DET_STR0 after (TCQ)*1 ps; 00255 else 00256 reg_state_eios_det <= EIOS_DET_IDL after (TCQ)*1 ps; 00257 end if; 00258 00259 when EIOS_DET_NO_STR0 => 00260 if ((gt_rxcharisk_q(0) = '1') and (gt_rxdata_q(7 downto 0) = EIOS_IDL) and (gt_rxcharisk_q(1) = '1') and (gt_rxdata_q(15 downto 8) = EIOS_IDL)) then 00261 reg_state_eios_det <= EIOS_DET_DONE after (TCQ)*1 ps; 00262 else 00263 reg_state_eios_det <= EIOS_DET_IDL after (TCQ)*1 ps; 00264 end if; 00265 00266 when EIOS_DET_STR0 => 00267 if ((gt_rxcharisk_q(0) = '1') and (gt_rxdata_q(7 downto 0) = EIOS_IDL) and (gt_rxcharisk_q(1) = '1') and (gt_rxdata_q(15 downto 8) = EIOS_IDL)) then 00268 reg_state_eios_det <= EIOS_DET_STR1 after (TCQ)*1 ps; 00269 reg_eios_detected <= '1' after (TCQ)*1 ps; 00270 reg_symbol_after_eios <= '1' after (TCQ)*1 ps; 00271 else 00272 reg_state_eios_det <= EIOS_DET_IDL after (TCQ)*1 ps; 00273 end if; 00274 00275 when EIOS_DET_STR1 => 00276 if ((gt_rxcharisk_q(0) = '1') and (gt_rxdata_q(7 downto 0) = EIOS_IDL)) then 00277 reg_state_eios_det <= EIOS_DET_DONE after (TCQ)*1 ps; 00278 else 00279 reg_state_eios_det <= EIOS_DET_IDL after (TCQ)*1 ps; 00280 end if; 00281 00282 when EIOS_DET_DONE => 00283 reg_state_eios_det <= EIOS_DET_IDL after (TCQ)*1 ps; 00284 00285 when others => 00286 reg_state_eios_det <= EIOS_DET_IDL after (TCQ)*1 ps; 00287 end case; 00288 end if; 00289 end if; 00290 end process; 00291 00292 state_eios_det <= reg_state_eios_det; 00293 eios_detected <= reg_eios_detected; 00294 symbol_after_eios <= reg_symbol_after_eios; 00295 00296 -- user_rxvalid generation 00297 00298 process (USER_CLK) 00299 begin 00300 if (USER_CLK'event and USER_CLK = '1') then 00301 00302 if (RESET = '1') then 00303 reg_state_rxvld_ei <= USER_RXVLD_IDL after (TCQ)*1 ps; 00304 else 00305 case state_rxvld_ei is 00306 00307 when USER_RXVLD_IDL => 00308 if (eios_detected = '1') then 00309 reg_state_rxvld_ei <= USER_RXVLD_EI after (TCQ)*1 ps; 00310 else 00311 reg_state_rxvld_ei <= USER_RXVLD_IDL after (TCQ)*1 ps; 00312 end if; 00313 00314 when USER_RXVLD_EI => 00315 if ((not(gt_rxvalid_q)) = '1') then 00316 reg_state_rxvld_ei <= USER_RXVLD_EI_DB0 after (TCQ)*1 ps; 00317 elsif (rxvld_fallback = "1111") then 00318 reg_state_rxvld_ei <= USER_RXVLD_IDL after (TCQ)*1 ps; 00319 else 00320 reg_state_rxvld_ei <= USER_RXVLD_EI after (TCQ)*1 ps; 00321 end if; 00322 00323 when USER_RXVLD_EI_DB0 => 00324 if (gt_rxvalid_q = '1') then 00325 reg_state_rxvld_ei <= USER_RXVLD_EI_DB1 after (TCQ)*1 ps; 00326 elsif ((not(PLM_IN_L0)) = '1') then 00327 reg_state_rxvld_ei <= USER_RXVLD_IDL after (TCQ)*1 ps; 00328 else 00329 reg_state_rxvld_ei <= USER_RXVLD_EI_DB0 after (TCQ)*1 ps; 00330 end if; 00331 00332 when USER_RXVLD_EI_DB1 => 00333 if (rxvld_count > to_stdlogicvector(CLK_COR_MIN_LAT, 5)) then 00334 reg_state_rxvld_ei <= USER_RXVLD_IDL after (TCQ)*1 ps; 00335 else 00336 reg_state_rxvld_ei <= USER_RXVLD_EI_DB1 after (TCQ)*1 ps; 00337 end if; 00338 when others => 00339 reg_state_rxvld_ei <= USER_RXVLD_IDL after (TCQ)*1 ps; 00340 end case; 00341 end if; 00342 end if; 00343 end process; 00344 00345 00346 state_rxvld_ei <= reg_state_rxvld_ei; 00347 00348 -- RxValid counter 00349 00350 process (USER_CLK) 00351 begin 00352 if (USER_CLK'event and USER_CLK = '1') then 00353 00354 if (RESET = '1') then 00355 reg_rxvld_count <= "00000" after (TCQ)*1 ps; 00356 else 00357 00358 if ((gt_rxvalid_q = '1') and (state_rxvld_ei = USER_RXVLD_EI_DB1)) then 00359 reg_rxvld_count <= reg_rxvld_count + "00001" after (TCQ)*1 ps; 00360 else 00361 reg_rxvld_count <= "00000" after (TCQ)*1 ps; 00362 end if; 00363 00364 end if; 00365 end if; 00366 end process; 00367 00368 00369 rxvld_count <= reg_rxvld_count; 00370 00371 -- RxValid fallback 00372 00373 process (USER_CLK) 00374 begin 00375 if (USER_CLK'event and USER_CLK = '1') then 00376 if (RESET = '1') then 00377 reg_rxvld_fallback <= "0000" after (TCQ)*1 ps; 00378 else 00379 if (state_rxvld_ei = USER_RXVLD_EI) then 00380 reg_rxvld_fallback <= reg_rxvld_fallback + "0001" after (TCQ)*1 ps; 00381 else 00382 reg_rxvld_fallback <= "0000" after (TCQ)*1 ps; 00383 end if; 00384 end if; 00385 end if; 00386 end process; 00387 00388 rxvld_fallback <= reg_rxvld_fallback; 00389 00390 -- Delay pipe_rx_elec_idle 00391 00392 rx_elec_idle_delay : SRL16E 00393 generic map ( 00394 INIT => X"0000" 00395 ) 00396 port map ( 00397 Q => USER_RXELECIDLE_v6pcie0, 00398 D => gt_rxelecidle_q, 00399 CLK => USER_CLK, 00400 CE => '1', 00401 A3 => '1', 00402 A2 => '1', 00403 A1 => '1', 00404 A0 => '1' 00405 ); 00406 00407 awake_see_com_0 <= GT_RXVALID and (gt_rxcharisk_q(0) and to_stdlogic(gt_rxdata_q(7 downto 0) = EIOS_COM)); 00408 00409 awake_see_com_1 <= GT_RXVALID and (gt_rxcharisk_q(1) and to_stdlogic(gt_rxdata_q(15 downto 8) = EIOS_COM)); 00410 00411 awake_see_com <= (awake_see_com_0 or awake_see_com_1) and not(awake_see_com_q); 00412 00413 -- Count 8 COMs, (not back-to-back), when waking up from electrical idle 00414 -- but not for L0s (which is L0). 00415 00416 awake_done <= awake_in_progress_q and to_stdlogic(awake_com_count_q(3 downto 0) >= X"b"); 00417 00418 awake_start <= (not(gt_rxelecidle_q) and gt_rxelecidle_qq) or PLM_IN_RS; 00419 00420 awake_in_progress <= awake_start or (not(awake_done) and awake_in_progress_q); 00421 00422 awake_com_count_inced <= awake_com_count_q(3 downto 0) + "0001"; 00423 00424 awake_com_count <= "0000" when (not(awake_in_progress_q) = '1') else 00425 "0000" when (awake_start = '1') else 00426 awake_com_count_inced(3 downto 0) when (awake_see_com_q = '1') else 00427 awake_com_count_q(3 downto 0); 00428 00429 rst_l <= not(RESET); 00430 00431 process (USER_CLK) 00432 begin 00433 if (USER_CLK'event and USER_CLK = '1') then 00434 if (rst_l = '0') then 00435 awake_see_com_q <= '0'; 00436 awake_in_progress_q <= '0'; 00437 awake_com_count_q(3 downto 0) <= "0000"; 00438 else 00439 awake_see_com_q <= awake_see_com; 00440 awake_in_progress_q <= awake_in_progress; 00441 awake_com_count_q(3 downto 0) <= awake_com_count(3 downto 0); 00442 end if; 00443 end if; 00444 end process; 00445 00446 USER_RXVALID_v6pcie1 <= gt_rxvalid_q when ((state_rxvld_ei = USER_RXVLD_IDL) and (not(awake_in_progress_q) = '1')) else 00447 '0'; 00448 USER_RXCHARISK(0) <= gt_rxcharisk_q(0) when (USER_RXVALID_v6pcie1 = '1') else 00449 '0'; 00450 USER_RXCHARISK(1) <= gt_rxcharisk_q(1) when ((USER_RXVALID_v6pcie1 and not(symbol_after_eios)) = '1') else 00451 '0'; 00452 USER_RXDATA(7 downto 0) <= FTSOS_COM when (gt_rx_is_skp0_q = '1') else 00453 gt_rxdata_q(7 downto 0); 00454 00455 USER_RXDATA(15 downto 8) <= FTSOS_COM when (gt_rx_is_skp1_q = '1') else 00456 gt_rxdata_q(15 downto 8); 00457 00458 USER_RX_STATUS <= gt_rx_status_q when (state_rxvld_ei = USER_RXVLD_IDL) else 00459 "000"; 00460 USER_RX_PHY_STATUS <= gt_rx_phy_status_q; 00461 00462 end v6_pcie; 00463 00464
1.7.4