DS_DMA
|
Architectures | |
v6_pcie | Architecture |
Libraries | |
ieee | |
unisim | |
Packages | |
std_logic_1164 | |
std_logic_unsigned | |
vcomponents | |
Generics | |
CLK_COR_MIN_LAT | integer := 28 |
Ports | |
USER_RXCHARISK | out std_logic_vector ( 1 downto 0 ) |
USER_RXDATA | out std_logic_vector ( 15 downto 0 ) |
USER_RXVALID | out std_logic |
USER_RXELECIDLE | out std_logic |
USER_RX_STATUS | out std_logic_vector ( 2 downto 0 ) |
USER_RX_PHY_STATUS | out std_logic |
GT_RXCHARISK | in std_logic_vector ( 1 downto 0 ) |
GT_RXDATA | in std_logic_vector ( 15 downto 0 ) |
GT_RXVALID | in std_logic |
GT_RXELECIDLE | in std_logic |
GT_RX_STATUS | in std_logic_vector ( 2 downto 0 ) |
GT_RX_PHY_STATUS | in std_logic |
PLM_IN_L0 | in std_logic |
PLM_IN_RS | in std_logic |
USER_CLK | in std_logic |
RESET | in std_logic |
См. определение в файле gtx_rx_valid_filter_v6.vhd строка 62