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DS_DMA
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00001 00002 ------------------------------------------------------------------------------- 00003 -- 00004 -- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved. 00005 -- 00006 -- This file contains confidential and proprietary information 00007 -- of Xilinx, Inc. and is protected under U.S. and 00008 -- international copyright and other intellectual property 00009 -- laws. 00010 -- 00011 -- DISCLAIMER 00012 -- This disclaimer is not a license and does not grant any 00013 -- rights to the materials distributed herewith. Except as 00014 -- otherwise provided in a valid license issued to you by 00015 -- Xilinx, and to the maximum extent permitted by applicable 00016 -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 00017 -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 00018 -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 00019 -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 00020 -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 00021 -- (2) Xilinx shall not be liable (whether in contract or tort, 00022 -- including negligence, or under any other theory of 00023 -- liability) for any loss or damage of any kind or nature 00024 -- related to, arising under or in connection with these 00025 -- materials, including for any direct, or any indirect, 00026 -- special, incidental, or consequential loss or damage 00027 -- (including loss of data, profits, goodwill, or any type of 00028 -- loss or damage suffered as a result of any action brought 00029 -- by a third party) even if such damage or loss was 00030 -- reasonably foreseeable or Xilinx had been advised of the 00031 -- possibility of the same. 00032 -- 00033 -- CRITICAL APPLICATIONS 00034 -- Xilinx products are not designed or intended to be fail- 00035 -- safe, or for use in any application requiring fail-safe 00036 -- performance, such as life-support or safety devices or 00037 -- systems, Class III medical devices, nuclear facilities, 00038 -- applications related to the deployment of airbags, or any 00039 -- other applications that could lead to death, personal 00040 -- injury, or severe property or environmental damage 00041 -- (individually and collectively, "Critical 00042 -- Applications"). Customer assumes the sole risk and 00043 -- liability of any use of Xilinx products in Critical 00044 -- Applications, subject only to applicable laws and 00045 -- regulations governing limitations on product liability. 00046 -- 00047 -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 00048 -- PART OF THIS FILE AT ALL TIMES. 00049 -- 00050 ------------------------------------------------------------------------------- 00051 -- Project : Virtex-6 Integrated Block for PCI Express 00052 -- File : gtx_tx_sync_rate_v6.vhd 00053 -- Version : 2.3 00054 -- 00055 -- Module TX_SYNC 00056 -- 00057 ------------------------------------------------------------------------------- 00058 library ieee; 00059 use ieee.std_logic_1164.all; 00060 use ieee.std_logic_unsigned.all; 00061 00062 -- Module TX_SYNC 00063 00064 entity GTX_TX_SYNC_RATE_V6 is 00065 generic ( 00066 C_SIMULATION : integer := 0 -- Set to 1 for simulation 00067 00068 ); 00069 port ( 00070 ENPMAPHASEALIGN : out std_logic; 00071 PMASETPHASE : out std_logic; 00072 SYNC_DONE : out std_logic; 00073 OUT_DIV_RESET : out std_logic; 00074 PCS_RESET : out std_logic; 00075 USER_PHYSTATUS : out std_logic; 00076 TXALIGNDISABLE : out std_logic; 00077 DELAYALIGNRESET : out std_logic; 00078 USER_CLK : in std_logic; 00079 RESET : in std_logic; 00080 RATE : in std_logic; 00081 RATEDONE : in std_logic; 00082 GT_PHYSTATUS : in std_logic; 00083 RESETDONE : in std_logic 00084 ); 00085 end GTX_TX_SYNC_RATE_V6; 00086 00087 architecture v6_pcie of GTX_TX_SYNC_RATE_V6 is 00088 00089 constant TCQ : integer := 1; 00090 00091 FUNCTION to_stdlogic ( 00092 in_val : IN boolean) RETURN std_logic IS 00093 BEGIN 00094 IF (in_val) THEN 00095 RETURN('1'); 00096 ELSE 00097 RETURN('0'); 00098 END IF; 00099 END to_stdlogic; 00100 00101 constant IDLE : std_logic_vector(24 downto 0) := "0000000000000000000000001"; 00102 constant PHASEALIGN : std_logic_vector(24 downto 0) := "0000000000000000000000010"; 00103 constant RATECHANGE_DIVRESET : std_logic_vector(24 downto 0) := "0000000000000000000000100"; 00104 constant RATECHANGE_DIVRESET_POST : std_logic_vector(24 downto 0) := "0000000000000000000001000"; 00105 constant RATECHANGE_ENPMADISABLE : std_logic_vector(24 downto 0) := "0000000000000000000010000"; 00106 constant RATECHANGE_ENPMADISABLE_POST : std_logic_vector(24 downto 0) := "0000000000000000000100000"; 00107 constant RATECHANGE_PMARESET : std_logic_vector(24 downto 0) := "0000000000000000001000000"; 00108 constant RATECHANGE_IDLE : std_logic_vector(24 downto 0) := "0000000000000000010000000"; 00109 constant RATECHANGE_PCSRESET : std_logic_vector(24 downto 0) := "0000000000000000100000000"; 00110 constant RATECHANGE_PCSRESET_POST : std_logic_vector(24 downto 0) := "0000000000000001000000000"; 00111 constant RATECHANGE_ASSERTPHY : std_logic_vector(24 downto 0) := "0000000000000010000000000"; 00112 constant RESET_STATE : std_logic_vector(24 downto 0) := "0000000000000100000000000"; 00113 constant WAIT_PHYSTATUS : std_logic_vector(24 downto 0) := "0000000000010000000000000"; 00114 constant RATECHANGE_PMARESET_POST : std_logic_vector(24 downto 0) := "0000000000100000000000000"; 00115 constant RATECHANGE_DISABLEPHASE : std_logic_vector(24 downto 0) := "0000000001000000000000000"; 00116 constant DELAYALIGNRST : std_logic_vector(24 downto 0) := "0000000010000000000000000"; 00117 constant SETENPMAPHASEALIGN : std_logic_vector(24 downto 0) := "0000000100000000000000000"; 00118 constant TXALIGNDISABLEDEASSERT : std_logic_vector(24 downto 0) := "0000001000000000000000000"; 00119 constant RATECHANGE_TXDLYALIGNDISABLE : std_logic_vector(24 downto 0) := "0000010000000000000000000"; 00120 constant GTXTEST_PULSE_1 : std_logic_vector(24 downto 0) := "0000100000000000000000000"; 00121 constant RATECHANGE_DISABLE_TXALIGNDISABLE : std_logic_vector(24 downto 0) := "0001000000000000000000000"; 00122 constant BEFORE_GTXTEST_PULSE1_1024CLKS : std_logic_vector(24 downto 0) := "0010000000000000000000000"; 00123 constant BETWEEN_GTXTEST_PULSES : std_logic_vector(24 downto 0) := "0100000000000000000000000"; 00124 constant GTXTEST_PULSE_2 : std_logic_vector(24 downto 0) := "1000000000000000000000000"; 00125 00126 function s_idx( 00127 constant C_SIMULATION : integer) 00128 return integer is 00129 variable sidx_out : integer := 8; 00130 begin -- s_idx 00131 00132 if (C_SIMULATION /= 0) then 00133 sidx_out := 0; 00134 else 00135 sidx_out := 2; 00136 end if; 00137 return sidx_out; 00138 end s_idx; 00139 00140 function pma_idx( 00141 constant C_SIMULATION : integer) 00142 return integer is 00143 variable pma_idx_out : integer := 8; 00144 begin -- pma_idx 00145 00146 if (C_SIMULATION /= 0) then 00147 pma_idx_out := 0; 00148 else 00149 pma_idx_out := 7; 00150 end if; 00151 return pma_idx_out; 00152 end pma_idx; 00153 00154 constant SYNC_IDX : integer := s_idx(C_SIMULATION); 00155 constant PMARESET_IDX : integer := pma_idx(C_SIMULATION); 00156 00157 signal ENPMAPHASEALIGN_c : std_logic; 00158 signal PMASETPHASE_c : std_logic; 00159 signal SYNC_DONE_c : std_logic; 00160 signal OUT_DIV_RESET_c : std_logic; 00161 signal PCS_RESET_c : std_logic; 00162 signal USER_PHYSTATUS_c : std_logic; 00163 signal DELAYALIGNRESET_c : std_logic; 00164 signal TXALIGNDISABLE_c : std_logic; 00165 signal state : std_logic_vector(24 downto 0); 00166 signal nextstate : std_logic_vector(24 downto 0); 00167 signal wait_amt : std_logic_vector(15 downto 0); 00168 signal wait_c : std_logic_vector(15 downto 0); 00169 signal waitcounter : std_logic_vector(7 downto 0); 00170 signal nextwaitcounter : std_logic_vector(7 downto 0); 00171 signal waitcounter2 : std_logic_vector(7 downto 0); 00172 signal waitcounter2_check : std_logic_vector(7 downto 0); 00173 signal nextwaitcounter2 : std_logic_vector(7 downto 0); 00174 signal ratedone_r : std_logic; 00175 signal ratedone_r2 : std_logic; 00176 signal ratedone_pulse_i : std_logic; 00177 00178 signal gt_phystatus_q : std_logic; 00179 00180 -- Declare intermediate signals for referenced outputs 00181 signal state_v6pcie0 : std_logic_vector(4 downto 0); 00182 -- signal waitcounter_v6pcie1 : std_logic_vector(16 downto 0); 00183 00184 begin 00185 00186 -- Drive referenced outputs 00187 -- state <= state_v6pcie0; 00188 -- waitcounter <= waitcounter_v6pcie1; 00189 00190 process (USER_CLK) 00191 begin 00192 if (USER_CLK'event and USER_CLK = '1') then 00193 00194 if (RESET = '1') then 00195 00196 state <= RESET_STATE after (TCQ)*1 ps; 00197 waitcounter <= X"00" after (TCQ)*1 ps; 00198 waitcounter2 <= X"00" after (TCQ)*1 ps; 00199 USER_PHYSTATUS <= GT_PHYSTATUS after (TCQ)*1 ps; 00200 SYNC_DONE <= '0' after (TCQ)*1 ps; 00201 ENPMAPHASEALIGN <= '0' after (TCQ)*1 ps; 00202 PMASETPHASE <= '0' after (TCQ)*1 ps; 00203 OUT_DIV_RESET <= '0' after (TCQ)*1 ps; 00204 PCS_RESET <= '0' after (TCQ)*1 ps; 00205 DELAYALIGNRESET <= '0' after (TCQ)*1 ps; 00206 TXALIGNDISABLE <= '1' after (TCQ)*1 ps; 00207 00208 else 00209 00210 state <= nextstate after (TCQ)*1 ps; 00211 waitcounter <= nextwaitcounter after (TCQ)*1 ps; 00212 waitcounter2 <= nextwaitcounter2 after (TCQ)*1 ps; 00213 USER_PHYSTATUS <= USER_PHYSTATUS_c after (TCQ)*1 ps; 00214 SYNC_DONE <= SYNC_DONE_c after (TCQ)*1 ps; 00215 ENPMAPHASEALIGN <= ENPMAPHASEALIGN_c after (TCQ)*1 ps; 00216 PMASETPHASE <= PMASETPHASE_c after (TCQ)*1 ps; 00217 OUT_DIV_RESET <= OUT_DIV_RESET_c after (TCQ)*1 ps; 00218 PCS_RESET <= PCS_RESET_c after (TCQ)*1 ps; 00219 DELAYALIGNRESET <= DELAYALIGNRESET_c after (TCQ)*1 ps; 00220 TXALIGNDISABLE <= TXALIGNDISABLE_c after (TCQ)*1 ps; 00221 00222 end if; 00223 end if; 00224 end process; 00225 00226 waitcounter2_check <= waitcounter2 + X"01" when (waitcounter = X"FF") else 00227 waitcounter2; 00228 00229 process (state, GT_PHYSTATUS, waitcounter, waitcounter2, waitcounter2_check, ratedone_pulse_i, gt_phystatus_q, RESETDONE) 00230 begin 00231 00232 -- DEFAULT CONDITIONS 00233 00234 DELAYALIGNRESET_c <= '0'; 00235 SYNC_DONE_c <= '0'; 00236 ENPMAPHASEALIGN_c <= '1'; 00237 PMASETPHASE_c <= '0'; 00238 OUT_DIV_RESET_c <= '0'; 00239 PCS_RESET_c <= '0'; 00240 TXALIGNDISABLE_c <= '0'; 00241 nextstate <= state; 00242 USER_PHYSTATUS_c <= GT_PHYSTATUS; 00243 00244 nextwaitcounter <= waitcounter + X"01"; 00245 nextwaitcounter2 <= waitcounter2_check; 00246 00247 case state is 00248 00249 -- START IN RESET 00250 when RESET_STATE => 00251 TXALIGNDISABLE_c <= '1'; 00252 ENPMAPHASEALIGN_c <= '0'; 00253 nextstate <= BEFORE_GTXTEST_PULSE1_1024CLKS; 00254 nextwaitcounter <= X"00"; 00255 nextwaitcounter2 <= X"00"; 00256 00257 -- Wait 1024 clocks before asseting GTXTEST[1] - Figure 3-9 UG366 00258 when BEFORE_GTXTEST_PULSE1_1024CLKS => 00259 OUT_DIV_RESET_c <= '0'; 00260 TXALIGNDISABLE_c <= '1'; 00261 ENPMAPHASEALIGN_c <= '0'; 00262 if ((waitcounter2(1)) = '1') then 00263 nextstate <= GTXTEST_PULSE_1; 00264 nextwaitcounter <= X"00"; 00265 nextwaitcounter2 <= X"00"; 00266 end if; 00267 00268 -- Assert GTXTEST[1] for 256 clocks - Figure 3-9 UG366 00269 when GTXTEST_PULSE_1 => 00270 OUT_DIV_RESET_c <= '1'; 00271 TXALIGNDISABLE_c <= '1'; 00272 ENPMAPHASEALIGN_c <= '0'; 00273 if ((waitcounter(7)) = '1') then 00274 nextstate <= BETWEEN_GTXTEST_PULSES; 00275 nextwaitcounter <= X"00"; 00276 nextwaitcounter2 <= X"00"; 00277 end if; 00278 00279 -- De-assert GTXTEST[1] for 256 clocks - Figure 3-9 UG366 00280 when BETWEEN_GTXTEST_PULSES => 00281 OUT_DIV_RESET_c <= '0'; 00282 TXALIGNDISABLE_c <= '1'; 00283 ENPMAPHASEALIGN_c <= '0'; 00284 if ((waitcounter(7)) = '1') then 00285 nextstate <= GTXTEST_PULSE_2; 00286 nextwaitcounter <= X"00"; 00287 nextwaitcounter2 <= X"00"; 00288 end if; 00289 00290 -- Assert GTXTEST[1] for 256 clocks - Figure 3-9 UG366 00291 when GTXTEST_PULSE_2 => 00292 OUT_DIV_RESET_c <= '1'; 00293 TXALIGNDISABLE_c <= '1'; 00294 ENPMAPHASEALIGN_c <= '0'; 00295 if ((waitcounter(7)) = '1') then 00296 nextstate <= DELAYALIGNRST; 00297 nextwaitcounter <= X"00"; 00298 nextwaitcounter2 <= X"00"; 00299 end if; 00300 00301 00302 -- ASSERT TXDLYALIGNRESET FOR 16 CLOCK CYCLES 00303 when DELAYALIGNRST => 00304 DELAYALIGNRESET_c <= '1'; 00305 ENPMAPHASEALIGN_c <= '0'; 00306 TXALIGNDISABLE_c <= '1'; 00307 if ((waitcounter(4)) = '1') then 00308 nextstate <= SETENPMAPHASEALIGN; 00309 nextwaitcounter <= X"00"; 00310 nextwaitcounter2 <= X"00"; 00311 end if; 00312 00313 -- ASSERT ENPMAPHASEALIGN FOR 32 CLOCK CYCLES 00314 when SETENPMAPHASEALIGN => 00315 TXALIGNDISABLE_c <= '1'; 00316 if ((waitcounter(5)) = '1') then 00317 nextstate <= PHASEALIGN; 00318 nextwaitcounter <= X"00"; 00319 nextwaitcounter2 <= X"00"; 00320 end if; 00321 00322 -- ASSERT PMASETPHASE OUT OF RESET for 32K CYCLES 00323 when PHASEALIGN => 00324 PMASETPHASE_c <= '1'; 00325 TXALIGNDISABLE_c <= '1'; 00326 if ((waitcounter2(PMARESET_IDX)) = '1') then 00327 nextstate <= TXALIGNDISABLEDEASSERT; 00328 nextwaitcounter <= X"00"; 00329 nextwaitcounter2 <= X"00"; 00330 end if; 00331 00332 -- KEEP TXALIGNDISABLE ASSERTED for 64 CYCLES 00333 when TXALIGNDISABLEDEASSERT => 00334 TXALIGNDISABLE_c <= '1'; 00335 if ((waitcounter(6)) = '1') then 00336 nextwaitcounter <= X"00"; 00337 nextstate <= IDLE; 00338 nextwaitcounter2 <= X"00"; 00339 end if; 00340 00341 -- NOW IN IDLE, ASSERT SYNC DONE, WAIT FOR RATECHANGE 00342 when IDLE => 00343 SYNC_DONE_c <= '1'; 00344 if (ratedone_pulse_i = '1') then 00345 USER_PHYSTATUS_c <= '0'; 00346 nextstate <= WAIT_PHYSTATUS; 00347 nextwaitcounter <= X"00"; 00348 nextwaitcounter2 <= X"00"; 00349 end if; 00350 00351 -- WAIT FOR PHYSTATUS 00352 when WAIT_PHYSTATUS => 00353 USER_PHYSTATUS_c <= '0'; 00354 if (gt_phystatus_q = '1') then 00355 nextstate <= RATECHANGE_IDLE; 00356 nextwaitcounter <= X"00"; 00357 nextwaitcounter2 <= X"00"; 00358 end if; 00359 00360 -- WAIT 64 CYCLES BEFORE WE START THE RATE CHANGE 00361 when RATECHANGE_IDLE => 00362 USER_PHYSTATUS_c <= '0'; 00363 if ((waitcounter(6)) = '1') then 00364 nextstate <= RATECHANGE_TXDLYALIGNDISABLE; 00365 nextwaitcounter <= X"00"; 00366 nextwaitcounter2 <= X"00"; 00367 end if; 00368 00369 -- ASSERT TXALIGNDISABLE FOR 32 CYCLES 00370 when RATECHANGE_TXDLYALIGNDISABLE => 00371 USER_PHYSTATUS_c <= '0'; 00372 TXALIGNDISABLE_c <= '1'; 00373 if ((waitcounter(5)) = '1') then 00374 nextstate <= RATECHANGE_DIVRESET; 00375 nextwaitcounter <= X"00"; 00376 nextwaitcounter2 <= X"00"; 00377 end if; 00378 00379 -- ASSERT DIV RESET FOR 16 CLOCK CYCLES 00380 when RATECHANGE_DIVRESET => 00381 OUT_DIV_RESET_c <= '1'; 00382 USER_PHYSTATUS_c <= '0'; 00383 TXALIGNDISABLE_c <= '1'; 00384 if ((waitcounter(4)) = '1') then 00385 nextstate <= RATECHANGE_DIVRESET_POST; 00386 nextwaitcounter <= X"00"; 00387 nextwaitcounter2 <= X"00"; 00388 end if; 00389 00390 -- WAIT FOR 32 CLOCK CYCLES BEFORE NEXT STEP 00391 when RATECHANGE_DIVRESET_POST => 00392 USER_PHYSTATUS_c <= '0'; 00393 TXALIGNDISABLE_c <= '1'; 00394 if ((waitcounter(5)) = '1') then 00395 nextstate <= RATECHANGE_PMARESET; 00396 nextwaitcounter <= X"00"; 00397 nextwaitcounter2 <= X"00"; 00398 end if; 00399 00400 -- ASSERT PMA RESET FOR 32K CYCLES 00401 when RATECHANGE_PMARESET => 00402 PMASETPHASE_c <= '1'; 00403 USER_PHYSTATUS_c <= '0'; 00404 TXALIGNDISABLE_c <= '1'; 00405 if ((waitcounter2(PMARESET_IDX)) = '1') then 00406 nextstate <= RATECHANGE_PMARESET_POST; 00407 nextwaitcounter <= X"00"; 00408 nextwaitcounter2 <= X"00"; 00409 end if; 00410 00411 -- WAIT FOR 32 CYCLES BEFORE DISABLING TXALIGNDISABLE 00412 when RATECHANGE_PMARESET_POST => 00413 USER_PHYSTATUS_c <= '0'; 00414 TXALIGNDISABLE_c <= '1'; 00415 if ((waitcounter(5)) = '1') then 00416 nextstate <= RATECHANGE_DISABLE_TXALIGNDISABLE; 00417 nextwaitcounter <= X"00"; 00418 nextwaitcounter2 <= X"00"; 00419 end if; 00420 00421 -- DISABLE TXALIGNDISABLE FOR 32 CYCLES 00422 when RATECHANGE_DISABLE_TXALIGNDISABLE => 00423 USER_PHYSTATUS_c <= '0'; 00424 if ((waitcounter(5)) = '1') then 00425 nextstate <= RATECHANGE_PCSRESET; 00426 nextwaitcounter <= X"00"; 00427 nextwaitcounter2 <= X"00"; 00428 end if; 00429 00430 -- NOW ASSERT PCS RESET FOR 32 CYCLES 00431 when RATECHANGE_PCSRESET => 00432 PCS_RESET_c <= '1'; 00433 USER_PHYSTATUS_c <= '0'; 00434 if ((waitcounter(5)) = '1') then 00435 nextstate <= RATECHANGE_PCSRESET_POST; 00436 nextwaitcounter <= X"00"; 00437 nextwaitcounter2 <= X"00"; 00438 end if; 00439 00440 -- WAIT FOR RESETDONE BEFORE ASSERTING PHY_STATUS_OUT 00441 when RATECHANGE_PCSRESET_POST => 00442 USER_PHYSTATUS_c <= '0'; 00443 if (RESETDONE = '1') then 00444 nextstate <= RATECHANGE_ASSERTPHY; 00445 end if; 00446 00447 -- ASSERT PHYSTATUSOUT MEANING RATECHANGE IS DONE AND GO BACK TO IDLE 00448 when RATECHANGE_ASSERTPHY => 00449 USER_PHYSTATUS_c <= '1'; 00450 nextstate <= IDLE; 00451 00452 when others => 00453 nextstate <= IDLE; 00454 00455 end case; 00456 end process; 00457 00458 00459 -- Generate Ratechange Pulse 00460 00461 process (USER_CLK) 00462 begin 00463 if (USER_CLK'event and USER_CLK = '1') then 00464 00465 if (RESET = '1') then 00466 00467 ratedone_r <= '0' after (TCQ)*1 ps; 00468 ratedone_r2 <= '0' after (TCQ)*1 ps; 00469 gt_phystatus_q <= '0' after (TCQ)*1 ps; 00470 00471 else 00472 00473 ratedone_r <= RATE after (TCQ)*1 ps; 00474 ratedone_r2 <= ratedone_r after (TCQ)*1 ps; 00475 gt_phystatus_q <= GT_PHYSTATUS after (TCQ)*1 ps; 00476 00477 end if; 00478 00479 end if; 00480 end process; 00481 00482 00483 ratedone_pulse_i <= to_stdlogic((ratedone_r /= ratedone_r2)); 00484 00485 end v6_pcie; 00486 00487
1.7.4