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DS_DMA
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00001 ------------------------------------------------------------------------------- 00002 -- 00003 -- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved. 00004 -- 00005 -- This file contains confidential and proprietary information 00006 -- of Xilinx, Inc. and is protected under U.S. and 00007 -- international copyright and other intellectual property 00008 -- laws. 00009 -- 00010 -- DISCLAIMER 00011 -- This disclaimer is not a license and does not grant any 00012 -- rights to the materials distributed herewith. Except as 00013 -- otherwise provided in a valid license issued to you by 00014 -- Xilinx, and to the maximum extent permitted by applicable 00015 -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 00016 -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 00017 -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 00018 -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 00019 -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 00020 -- (2) Xilinx shall not be liable (whether in contract or tort, 00021 -- including negligence, or under any other theory of 00022 -- liability) for any loss or damage of any kind or nature 00023 -- related to, arising under or in connection with these 00024 -- materials, including for any direct, or any indirect, 00025 -- special, incidental, or consequential loss or damage 00026 -- (including loss of data, profits, goodwill, or any type of 00027 -- loss or damage suffered as a result of any action brought 00028 -- by a third party) even if such damage or loss was 00029 -- reasonably foreseeable or Xilinx had been advised of the 00030 -- possibility of the same. 00031 -- 00032 -- CRITICAL APPLICATIONS 00033 -- Xilinx products are not designed or intended to be fail- 00034 -- safe, or for use in any application requiring fail-safe 00035 -- performance, such as life-support or safety devices or 00036 -- systems, Class III medical devices, nuclear facilities, 00037 -- applications related to the deployment of airbags, or any 00038 -- other applications that could lead to death, personal 00039 -- injury, or severe property or environmental damage 00040 -- (individually and collectively, "Critical 00041 -- Applications"). Customer assumes the sole risk and 00042 -- liability of any use of Xilinx products in Critical 00043 -- Applications, subject only to applicable laws and 00044 -- regulations governing limitations on product liability. 00045 -- 00046 -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 00047 -- PART OF THIS FILE AT ALL TIMES. 00048 -- 00049 ------------------------------------------------------------------------------- 00050 -- Project : Virtex-6 Integrated Block for PCI Express 00051 -- File : pcie_clocking_v6.vhd 00052 -- Version : 2.3 00053 ---- Description: Clocking module for Virtex6 PCIe Block 00054 ---- 00055 ---- 00056 ---- 00057 ---------------------------------------------------------------------------------- 00058 00059 library ieee; 00060 use ieee.std_logic_1164.all; 00061 00062 library unisim; 00063 use unisim.vcomponents.all; 00064 00065 entity pcie_clocking_v6 is 00066 generic ( 00067 00068 IS_ENDPOINT : boolean := TRUE; 00069 CAP_LINK_WIDTH : integer := 8; -- 1 - x1 , 2 - x2 , 4 - x4 , 8 - x8 00070 CAP_LINK_SPEED : integer := 1; -- 1 - Gen1 , 2 - Gen2 00071 REF_CLK_FREQ : integer := 0; -- 0 - 100 MHz , 1 - 125 MHz , 2 - 250 MHz 00072 USER_CLK_FREQ : integer := 3 -- 0 - 31.25 MHz , 1 - 62.5 MHz , 2 - 125 MHz , 3 - 250 MHz , 4 - 500Mhz 00073 00074 ); 00075 port ( 00076 sys_clk : in std_logic; 00077 gt_pll_lock : in std_logic; 00078 sel_lnk_rate : in std_logic; 00079 sel_lnk_width : in std_logic_vector(1 downto 0); 00080 sys_clk_bufg : out std_logic; 00081 pipe_clk : out std_logic; 00082 user_clk : out std_logic; 00083 block_clk : out std_logic; 00084 drp_clk : out std_logic; 00085 clock_locked : out std_logic 00086 ); 00087 end pcie_clocking_v6; 00088 00089 architecture v6_pcie of pcie_clocking_v6 is 00090 00091 -- MMCM Configuration 00092 00093 function clkin_prd( 00094 constant REF_CLK_FREQ : integer) 00095 return real is 00096 variable CLKIN_PERD : real := 0.0; 00097 begin -- clkin_prd 00098 00099 if (REF_CLK_FREQ = 0) then 00100 CLKIN_PERD := 10.0; 00101 elsif (REF_CLK_FREQ = 1) then 00102 CLKIN_PERD := 8.0; 00103 elsif (REF_CLK_FREQ = 2) then 00104 CLKIN_PERD := 4.0; 00105 else 00106 CLKIN_PERD := 0.0; 00107 end if; 00108 return CLKIN_PERD; 00109 end clkin_prd; 00110 00111 constant mmcm_clockin_period : real := clkin_prd(REF_CLK_FREQ); 00112 00113 function clkfb_mul( 00114 constant REF_CLK_FREQ : integer) 00115 return real is 00116 variable CLKFB_MULT : real := 0.0; 00117 begin -- clkfb_mul 00118 00119 if (REF_CLK_FREQ = 0) then 00120 CLKFB_MULT := 10.0; 00121 elsif (REF_CLK_FREQ = 1) then 00122 CLKFB_MULT := 8.0; 00123 elsif (REF_CLK_FREQ = 2) then 00124 CLKFB_MULT := 8.0; 00125 else 00126 CLKFB_MULT := 0.0; 00127 end if; 00128 return CLKFB_MULT; 00129 end clkfb_mul; 00130 00131 constant mmcm_clockfb_mult : real := clkfb_mul(REF_CLK_FREQ); 00132 00133 function divclk_div( 00134 constant REF_CLK_FREQ : integer) 00135 return integer is 00136 variable DIVCLK_DIVIDE : integer := 0; 00137 begin -- divclk_div 00138 00139 if (REF_CLK_FREQ = 0) then 00140 DIVCLK_DIVIDE := 1; 00141 elsif (REF_CLK_FREQ = 1) then 00142 DIVCLK_DIVIDE := 1; 00143 elsif (REF_CLK_FREQ = 2) then 00144 DIVCLK_DIVIDE := 2; 00145 else 00146 DIVCLK_DIVIDE := 0; 00147 end if; 00148 return DIVCLK_DIVIDE; 00149 end divclk_div; 00150 00151 constant mmcm_divclk_divide : integer := divclk_div(REF_CLK_FREQ); 00152 00153 constant mmcm_clock0_div : real := 4.0; 00154 constant mmcm_clock1_div : integer := 8; 00155 00156 constant TCQ : integer := 1; 00157 00158 function clk2_div( 00159 constant LNK_WDT : integer; 00160 constant LNK_SPD : integer; 00161 constant USR_CLK_FREQ : integer) 00162 return integer is 00163 variable CLK_DIV : integer := 1; 00164 begin -- clk2_div 00165 00166 if ((LNK_WDT = 1) and (LNK_SPD = 1) and (USR_CLK_FREQ = 0)) then 00167 CLK_DIV := 32; 00168 elsif ((LNK_WDT = 1) and (LNK_SPD = 1) and (USR_CLK_FREQ = 1)) then 00169 CLK_DIV := 16; 00170 elsif ((LNK_WDT = 1) and (LNK_SPD = 2) and (USR_CLK_FREQ = 1)) then 00171 CLK_DIV := 16; 00172 elsif ((LNK_WDT = 2) and (LNK_SPD = 1) and (USR_CLK_FREQ = 1)) then 00173 CLK_DIV := 16; 00174 else 00175 CLK_DIV := 2; 00176 end if; 00177 return CLK_DIV; 00178 end clk2_div; 00179 00180 constant mmcm_clock2_div : integer := clk2_div(CAP_LINK_WIDTH, CAP_LINK_SPEED, USER_CLK_FREQ); 00181 constant mmcm_clock3_div : integer := 2; 00182 00183 signal mmcm_locked : std_logic; 00184 signal mmcm_clkfbin : std_logic; 00185 signal mmcm_clkfbout : std_logic; 00186 signal mmcm_reset : std_logic; 00187 signal clk_500 : std_logic; 00188 signal clk_250 : std_logic; 00189 signal clk_125 : std_logic; 00190 signal user_clk_prebuf : std_logic; 00191 signal sel_lnk_rate_d : std_logic; 00192 signal reg_clock_locked : std_logic_vector(1 downto 0) := "11"; 00193 00194 -- Declare intermediate signals for referenced outputs 00195 signal sys_clk_bufg_v6pcie3 : std_logic; 00196 signal pipe_clk_v6pcie : std_logic; 00197 signal user_clk_v6pcie4 : std_logic; 00198 signal block_clk_v6pcie0 : std_logic; 00199 signal drp_clk_v6pcie1 : std_logic; 00200 00201 signal clock_locked_int : std_logic; 00202 00203 begin 00204 -- Drive referenced outputs 00205 sys_clk_bufg <= sys_clk_bufg_v6pcie3; 00206 pipe_clk <= pipe_clk_v6pcie; 00207 user_clk <= user_clk_v6pcie4; 00208 block_clk <= block_clk_v6pcie0; 00209 drp_clk <= drp_clk_v6pcie1; 00210 clock_locked <= clock_locked_int; 00211 clock_locked_int <= (not(reg_clock_locked(1))) and mmcm_locked; 00212 00213 00214 -- MMCM Reset 00215 mmcm_reset <= '0'; 00216 00217 -- PIPE Clock BUFG. 00218 00219 GEN1_LINK : if (CAP_LINK_SPEED = 1) generate 00220 pipe_clk_bufg : BUFG port map (O => pipe_clk_v6pcie, I => clk_125 ); 00221 00222 end generate; 00223 00224 GEN2_LINK : if (CAP_LINK_SPEED = 2) generate 00225 sel_lnk_rate_delay : SRL16E generic map ( INIT => X"0000" ) 00226 port map ( 00227 Q => sel_lnk_rate_d, 00228 D => sel_lnk_rate, 00229 CLK => pipe_clk_v6pcie, 00230 CE => clock_locked_int, 00231 A3 => '1', 00232 A2 => '1', 00233 A1 => '1', 00234 A0 => '1' 00235 ); 00236 00237 pipe_clk_bufgmux : BUFGMUX port map ( 00238 O => pipe_clk_v6pcie, 00239 I0 => clk_125, 00240 I1 => clk_250, 00241 S => sel_lnk_rate_d 00242 ); 00243 00244 end generate; 00245 ILLEGAL_LINK_SPEED : if ((CAP_LINK_SPEED /= 1) and (CAP_LINK_SPEED /= 2)) generate 00246 00247 --$display("Confiuration Error : CAP_LINK_SPEED = %d, must be either 1 or 2.", CAP_LINK_SPEED); 00248 --$finish; 00249 00250 end generate; 00251 00252 -- User Clock BUFG. 00253 x1_GEN1_31_25 : if ((CAP_LINK_WIDTH = 1) and (CAP_LINK_SPEED = 1) and (USER_CLK_FREQ = 0)) generate 00254 00255 user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => user_clk_prebuf ); 00256 00257 end generate; 00258 00259 x1_GEN1_62_50 : if ((CAP_LINK_WIDTH = 1) and (CAP_LINK_SPEED = 1) and (USER_CLK_FREQ = 1)) generate 00260 00261 user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => user_clk_prebuf ); 00262 00263 end generate; 00264 00265 x1_GEN1_125_00 : if ((CAP_LINK_WIDTH = 1) and (CAP_LINK_SPEED = 1) and (USER_CLK_FREQ = 2)) generate 00266 00267 user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_125 ); 00268 00269 end generate; 00270 00271 x1_GEN1_250_00 : if ((CAP_LINK_WIDTH = 1) and (CAP_LINK_SPEED = 1) and (USER_CLK_FREQ = 3)) generate 00272 00273 user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_250 ); 00274 00275 end generate; 00276 00277 x1_GEN2_62_50 : if ((CAP_LINK_WIDTH = 1) and (CAP_LINK_SPEED = 2) and (USER_CLK_FREQ = 1)) generate 00278 00279 user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => user_clk_prebuf ); 00280 00281 end generate; 00282 00283 x1_GEN2_125_00 : if ((CAP_LINK_WIDTH = 1) and (CAP_LINK_SPEED = 2) and (USER_CLK_FREQ = 2)) generate 00284 00285 user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_125 ); 00286 00287 end generate; 00288 00289 x1_GEN2_250_00 : if ((CAP_LINK_WIDTH = 1) and (CAP_LINK_SPEED = 2) and (USER_CLK_FREQ = 3)) generate 00290 00291 user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_250 ); 00292 00293 end generate; 00294 00295 x2_GEN1_62_50 : if ((CAP_LINK_WIDTH = 2) and (CAP_LINK_SPEED = 1) and (USER_CLK_FREQ = 1)) generate 00296 00297 user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => user_clk_prebuf ); 00298 00299 end generate; 00300 00301 x2_GEN1_125_00 : if ((CAP_LINK_WIDTH = 2) and (CAP_LINK_SPEED = 1) and (USER_CLK_FREQ = 2)) generate 00302 00303 user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_125 ); 00304 00305 end generate; 00306 00307 x2_GEN1_250_00 : if ((CAP_LINK_WIDTH = 2) and (CAP_LINK_SPEED = 1) and (USER_CLK_FREQ = 3)) generate 00308 00309 user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_250 ); 00310 00311 end generate; 00312 00313 x2_GEN2_125_00 : if ((CAP_LINK_WIDTH = 2) and (CAP_LINK_SPEED = 2) and (USER_CLK_FREQ = 2)) generate 00314 00315 user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_125 ); 00316 00317 end generate; 00318 00319 x2_GEN2_250_00 : if ((CAP_LINK_WIDTH = 2) and (CAP_LINK_SPEED = 2) and (USER_CLK_FREQ = 3)) generate 00320 00321 user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_250 ); 00322 00323 end generate; 00324 00325 x4_GEN1_125_00 : if ((CAP_LINK_WIDTH = 4) and (CAP_LINK_SPEED = 1) and (USER_CLK_FREQ = 2)) generate 00326 00327 user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_125 ); 00328 00329 end generate; 00330 00331 x4_GEN1_250_00 : if ((CAP_LINK_WIDTH = 4) and (CAP_LINK_SPEED = 1) and (USER_CLK_FREQ = 3)) generate 00332 00333 user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_250 ); 00334 00335 end generate; 00336 00337 x4_GEN2_250_00 : if ((CAP_LINK_WIDTH = 4) and (CAP_LINK_SPEED = 2) and (USER_CLK_FREQ = 3)) generate 00338 00339 user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_250 ); 00340 00341 end generate; 00342 00343 x8_GEN1_250_00 : if ((CAP_LINK_WIDTH = 8) and (CAP_LINK_SPEED = 1) and (USER_CLK_FREQ = 3)) generate 00344 00345 user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_250 ); 00346 00347 end generate; 00348 00349 x8_GEN2_250_00 : if ((CAP_LINK_WIDTH = 8) and (CAP_LINK_SPEED = 2) and (USER_CLK_FREQ = 4)) generate 00350 00351 user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_250 ); 00352 00353 block_clk_bufg : BUFG port map ( O => block_clk_v6pcie0, I => clk_500 ); 00354 00355 end generate; 00356 00357 -- v6pcie42 : if (not((CAP_LINK_WIDTH = 8) and (CAP_LINK_SPEED = 2) and (USER_CLK_FREQ = 4))) generate 00358 00359 --$display("Confiuration Error : Unsupported Link Width, Link Speed and User Clock Frequency Combination"); 00360 --$finish; 00361 00362 -- end generate; 00363 00364 -- DRP clk 00365 drp_clk_bufg_i : BUFG port map ( O => drp_clk_v6pcie1, I => clk_125 ); 00366 00367 -- Feedback BUFG. Required for Temp Compensation 00368 clkfbin_bufg_i : BUFG port map ( O => mmcm_clkfbin, I => mmcm_clkfbout ); 00369 00370 -- sys_clk BUFG. 00371 sys_clk_bufg_i : BUFG port map ( O => sys_clk_bufg_v6pcie3, I => sys_clk ); 00372 00373 mmcm_adv_i : MMCM_ADV 00374 generic map ( 00375 -- 5 for 100 MHz , 4 for 125 MHz , 2 for 250 MHz 00376 CLKFBOUT_MULT_F => mmcm_clockfb_mult, 00377 DIVCLK_DIVIDE => mmcm_divclk_divide, 00378 CLKFBOUT_PHASE => 0.0, 00379 -- 10 for 100 MHz, 4 for 250 MHz 00380 CLKIN1_PERIOD => mmcm_clockin_period, 00381 CLKIN2_PERIOD => mmcm_clockin_period, 00382 -- 500 MHz / mmcm_clockx_div 00383 CLKOUT0_DIVIDE_F => mmcm_clock0_div, 00384 CLKOUT0_PHASE => 0.0, 00385 CLKOUT1_DIVIDE => mmcm_clock1_div, 00386 CLKOUT1_PHASE => 0.0, 00387 CLKOUT2_DIVIDE => mmcm_clock2_div, 00388 CLKOUT2_PHASE => 0.0, 00389 CLKOUT3_DIVIDE => mmcm_clock3_div, 00390 CLKOUT3_PHASE => 0.0 00391 ) 00392 port map ( 00393 clkfbout => mmcm_clkfbout, 00394 clkout0 => clk_250, -- 250 MHz for pipe_clk 00395 clkout1 => clk_125, -- 125 MHz for pipe_clk 00396 clkout2 => user_clk_prebuf , -- user clk 00397 clkout3 => clk_500, 00398 clkout4 => open, 00399 clkout5 => open, 00400 clkout6 => open, 00401 do => open, 00402 drdy => open , 00403 clkfboutb => open , 00404 clkfbstopped => open, 00405 clkinstopped => open, 00406 clkout0b => open, 00407 clkout1b => open, 00408 clkout2b => open, 00409 clkout3b => open, 00410 psdone => open, 00411 locked => mmcm_locked, 00412 clkfbin => mmcm_clkfbin, 00413 clkin1 => sys_clk, 00414 clkin2 => '0', 00415 clkinsel => '1', 00416 daddr => "0000000", 00417 dclk => '0', 00418 den => '0', 00419 di => "0000000000000000" , 00420 dwe => '0', 00421 psen => '0', 00422 psincdec => '0', 00423 pwrdwn => '0', 00424 psclk => '0', 00425 rst => mmcm_reset 00426 ); 00427 00428 -- Synchronize MMCM locked output 00429 process (pipe_clk_v6pcie, gt_pll_lock) 00430 begin 00431 00432 if ((not(gt_pll_lock)) = '1') then 00433 00434 reg_clock_locked <= "11" after (TCQ)*1 ps; 00435 00436 elsif (pipe_clk_v6pcie'event and pipe_clk_v6pcie = '1') then 00437 00438 reg_clock_locked <= (reg_clock_locked(0) & '0') after (TCQ)*1 ps; 00439 00440 end if; 00441 end process; 00442 00443 end v6_pcie; 00444 00445 00446
1.7.4