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DS_DMA
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00001 ------------------------------------------------------------------------------- 00002 -- 00003 -- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved. 00004 -- 00005 -- This file contains confidential and proprietary information 00006 -- of Xilinx, Inc. and is protected under U.S. and 00007 -- international copyright and other intellectual property 00008 -- laws. 00009 -- 00010 -- DISCLAIMER 00011 -- This disclaimer is not a license and does not grant any 00012 -- rights to the materials distributed herewith. Except as 00013 -- otherwise provided in a valid license issued to you by 00014 -- Xilinx, and to the maximum extent permitted by applicable 00015 -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 00016 -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 00017 -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 00018 -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 00019 -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 00020 -- (2) Xilinx shall not be liable (whether in contract or tort, 00021 -- including negligence, or under any other theory of 00022 -- liability) for any loss or damage of any kind or nature 00023 -- related to, arising under or in connection with these 00024 -- materials, including for any direct, or any indirect, 00025 -- special, incidental, or consequential loss or damage 00026 -- (including loss of data, profits, goodwill, or any type of 00027 -- loss or damage suffered as a result of any action brought 00028 -- by a third party) even if such damage or loss was 00029 -- reasonably foreseeable or Xilinx had been advised of the 00030 -- possibility of the same. 00031 -- 00032 -- CRITICAL APPLICATIONS 00033 -- Xilinx products are not designed or intended to be fail- 00034 -- safe, or for use in any application requiring fail-safe 00035 -- performance, such as life-support or safety devices or 00036 -- systems, Class III medical devices, nuclear facilities, 00037 -- applications related to the deployment of airbags, or any 00038 -- other applications that could lead to death, personal 00039 -- injury, or severe property or environmental damage 00040 -- (individually and collectively, "Critical 00041 -- Applications"). Customer assumes the sole risk and 00042 -- liability of any use of Xilinx products in Critical 00043 -- Applications, subject only to applicable laws and 00044 -- regulations governing limitations on product liability. 00045 -- 00046 -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 00047 -- PART OF THIS FILE AT ALL TIMES. 00048 -- 00049 ------------------------------------------------------------------------------- 00050 -- Project : Virtex-6 Integrated Block for PCI Express 00051 -- File : pcie_gtx_v6.vhd 00052 -- Version : 2.3 00053 -- Description: GTX module for Virtex6 PCIe Block 00054 -- 00055 -- 00056 -- 00057 -------------------------------------------------------------------------------- 00058 00059 library ieee; 00060 use ieee.std_logic_1164.all; 00061 use ieee.std_logic_unsigned.all; 00062 00063 entity pcie_gtx_v6 is 00064 generic ( 00065 NO_OF_LANES : integer := 8; -- 1 - x1 , 2 - x2 , 4 - x4 , 8 - x8 00066 LINK_CAP_MAX_LINK_SPEED : bit_vector := X"1"; -- 1 - Gen1, 2 - Gen2 00067 REF_CLK_FREQ : integer := 0; -- 0 - 100 MHz , 1 - 125 MHz , 2 - 250 MHz 00068 PL_FAST_TRAIN : boolean := FALSE 00069 ); 00070 port ( 00071 -- Pipe Per-Link Signals 00072 pipe_tx_rcvr_det : in std_logic; 00073 pipe_tx_reset : in std_logic; 00074 pipe_tx_rate : in std_logic; 00075 pipe_tx_deemph : in std_logic; 00076 pipe_tx_margin : in std_logic_vector(2 downto 0); 00077 pipe_tx_swing : in std_logic; 00078 00079 -- Pipe Per-Lane Signals - Lane 0 00080 pipe_rx0_char_is_k : out std_logic_vector(1 downto 0); 00081 pipe_rx0_data : out std_logic_vector(15 downto 0); 00082 pipe_rx0_valid : out std_logic; 00083 pipe_rx0_chanisaligned : out std_logic; 00084 pipe_rx0_status : out std_logic_vector(2 downto 0); 00085 pipe_rx0_phy_status : out std_logic; 00086 pipe_rx0_elec_idle : out std_logic; 00087 pipe_rx0_polarity : in std_logic; 00088 pipe_tx0_compliance : in std_logic; 00089 pipe_tx0_char_is_k : in std_logic_vector(1 downto 0); 00090 pipe_tx0_data : in std_logic_vector(15 downto 0); 00091 pipe_tx0_elec_idle : in std_logic; 00092 pipe_tx0_powerdown : in std_logic_vector(1 downto 0); 00093 00094 -- Pipe Per-Lane Signals - Lane 1 00095 pipe_rx1_char_is_k : out std_logic_vector(1 downto 0); 00096 pipe_rx1_data : out std_logic_vector(15 downto 0); 00097 pipe_rx1_valid : out std_logic; 00098 pipe_rx1_chanisaligned : out std_logic; 00099 pipe_rx1_status : out std_logic_vector(2 downto 0); 00100 pipe_rx1_phy_status : out std_logic; 00101 pipe_rx1_elec_idle : out std_logic; 00102 pipe_rx1_polarity : in std_logic; 00103 pipe_tx1_compliance : in std_logic; 00104 pipe_tx1_char_is_k : in std_logic_vector(1 downto 0); 00105 pipe_tx1_data : in std_logic_vector(15 downto 0); 00106 pipe_tx1_elec_idle : in std_logic; 00107 pipe_tx1_powerdown : in std_logic_vector(1 downto 0); 00108 00109 -- Pipe Per-Lane Signals - Lane 2 00110 pipe_rx2_char_is_k : out std_logic_vector(1 downto 0); 00111 pipe_rx2_data : out std_logic_vector(15 downto 0); 00112 pipe_rx2_valid : out std_logic; 00113 pipe_rx2_chanisaligned : out std_logic; 00114 pipe_rx2_status : out std_logic_vector(2 downto 0); 00115 pipe_rx2_phy_status : out std_logic; 00116 pipe_rx2_elec_idle : out std_logic; 00117 pipe_rx2_polarity : in std_logic; 00118 pipe_tx2_compliance : in std_logic; 00119 pipe_tx2_char_is_k : in std_logic_vector(1 downto 0); 00120 pipe_tx2_data : in std_logic_vector(15 downto 0); 00121 pipe_tx2_elec_idle : in std_logic; 00122 pipe_tx2_powerdown : in std_logic_vector(1 downto 0); 00123 00124 -- Pipe Per-Lane Signals - Lane 3 00125 pipe_rx3_char_is_k : out std_logic_vector(1 downto 0); 00126 pipe_rx3_data : out std_logic_vector(15 downto 0); 00127 pipe_rx3_valid : out std_logic; 00128 pipe_rx3_chanisaligned : out std_logic; 00129 pipe_rx3_status : out std_logic_vector(2 downto 0); 00130 pipe_rx3_phy_status : out std_logic; 00131 pipe_rx3_elec_idle : out std_logic; 00132 pipe_rx3_polarity : in std_logic; 00133 pipe_tx3_compliance : in std_logic; 00134 pipe_tx3_char_is_k : in std_logic_vector(1 downto 0); 00135 pipe_tx3_data : in std_logic_vector(15 downto 0); 00136 pipe_tx3_elec_idle : in std_logic; 00137 pipe_tx3_powerdown : in std_logic_vector(1 downto 0); 00138 00139 -- Pipe Per-Lane Signals - Lane 4 00140 pipe_rx4_char_is_k : out std_logic_vector(1 downto 0); 00141 pipe_rx4_data : out std_logic_vector(15 downto 0); 00142 pipe_rx4_valid : out std_logic; 00143 pipe_rx4_chanisaligned : out std_logic; 00144 pipe_rx4_status : out std_logic_vector(2 downto 0); 00145 pipe_rx4_phy_status : out std_logic; 00146 pipe_rx4_elec_idle : out std_logic; 00147 pipe_rx4_polarity : in std_logic; 00148 pipe_tx4_compliance : in std_logic; 00149 pipe_tx4_char_is_k : in std_logic_vector(1 downto 0); 00150 pipe_tx4_data : in std_logic_vector(15 downto 0); 00151 pipe_tx4_elec_idle : in std_logic; 00152 pipe_tx4_powerdown : in std_logic_vector(1 downto 0); 00153 00154 -- Pipe Per-Lane Signals - Lane 5 00155 pipe_rx5_char_is_k : out std_logic_vector(1 downto 0); 00156 pipe_rx5_data : out std_logic_vector(15 downto 0); 00157 pipe_rx5_valid : out std_logic; 00158 pipe_rx5_chanisaligned : out std_logic; 00159 pipe_rx5_status : out std_logic_vector(2 downto 0); 00160 pipe_rx5_phy_status : out std_logic; 00161 pipe_rx5_elec_idle : out std_logic; 00162 pipe_rx5_polarity : in std_logic; 00163 pipe_tx5_compliance : in std_logic; 00164 pipe_tx5_char_is_k : in std_logic_vector(1 downto 0); 00165 pipe_tx5_data : in std_logic_vector(15 downto 0); 00166 pipe_tx5_elec_idle : in std_logic; 00167 pipe_tx5_powerdown : in std_logic_vector(1 downto 0); 00168 00169 -- Pipe Per-Lane Signals - Lane 6 00170 pipe_rx6_char_is_k : out std_logic_vector(1 downto 0); 00171 pipe_rx6_data : out std_logic_vector(15 downto 0); 00172 pipe_rx6_valid : out std_logic; 00173 pipe_rx6_chanisaligned : out std_logic; 00174 pipe_rx6_status : out std_logic_vector(2 downto 0); 00175 pipe_rx6_phy_status : out std_logic; 00176 pipe_rx6_elec_idle : out std_logic; 00177 pipe_rx6_polarity : in std_logic; 00178 pipe_tx6_compliance : in std_logic; 00179 pipe_tx6_char_is_k : in std_logic_vector(1 downto 0); 00180 pipe_tx6_data : in std_logic_vector(15 downto 0); 00181 pipe_tx6_elec_idle : in std_logic; 00182 pipe_tx6_powerdown : in std_logic_vector(1 downto 0); 00183 00184 -- Pipe Per-Lane Signals - Lane 7 00185 pipe_rx7_char_is_k : out std_logic_vector(1 downto 0); 00186 pipe_rx7_data : out std_logic_vector(15 downto 0); 00187 pipe_rx7_valid : out std_logic; 00188 pipe_rx7_chanisaligned : out std_logic; 00189 pipe_rx7_status : out std_logic_vector(2 downto 0); 00190 pipe_rx7_phy_status : out std_logic; 00191 pipe_rx7_elec_idle : out std_logic; 00192 pipe_rx7_polarity : in std_logic; 00193 pipe_tx7_compliance : in std_logic; 00194 pipe_tx7_char_is_k : in std_logic_vector(1 downto 0); 00195 pipe_tx7_data : in std_logic_vector(15 downto 0); 00196 pipe_tx7_elec_idle : in std_logic; 00197 pipe_tx7_powerdown : in std_logic_vector(1 downto 0); 00198 00199 -- PCI Express signals 00200 pci_exp_txn : out std_logic_vector((NO_OF_LANES - 1) downto 0); 00201 pci_exp_txp : out std_logic_vector((NO_OF_LANES - 1) downto 0); 00202 pci_exp_rxn : in std_logic_vector((NO_OF_LANES - 1) downto 0); 00203 pci_exp_rxp : in std_logic_vector((NO_OF_LANES - 1) downto 0); 00204 00205 -- Non PIPE signals 00206 sys_clk : in std_logic; 00207 sys_rst_n : in std_logic; 00208 pipe_clk : in std_logic; 00209 drp_clk : in std_logic; 00210 clock_locked : in std_logic; 00211 gt_pll_lock : out std_logic; 00212 pl_ltssm_state : in std_logic_vector(5 downto 0); 00213 phy_rdy_n : out std_logic; 00214 TxOutClk : out std_logic 00215 ); 00216 end pcie_gtx_v6; 00217 00218 architecture v6_pcie of pcie_gtx_v6 is 00219 component gtx_wrapper_v6 is 00220 generic ( 00221 NO_OF_LANES : integer := 1; 00222 REF_CLK_FREQ : integer := 0; 00223 PL_FAST_TRAIN : boolean := FALSE 00224 ); 00225 port ( 00226 TX : out std_logic_vector(NO_OF_LANES - 1 downto 0); 00227 TXN : out std_logic_vector(NO_OF_LANES - 1 downto 0); 00228 TxData : in std_logic_vector((NO_OF_LANES * 16) - 1 downto 0); 00229 TxDataK : in std_logic_vector((NO_OF_LANES * 2) - 1 downto 0); 00230 TxElecIdle : in std_logic_vector(NO_OF_LANES - 1 downto 0); 00231 TxCompliance : in std_logic_vector(NO_OF_LANES - 1 downto 0); 00232 RX : in std_logic_vector(NO_OF_LANES - 1 downto 0); 00233 RXN : in std_logic_vector(NO_OF_LANES - 1 downto 0); 00234 RxData : out std_logic_vector((NO_OF_LANES * 16) - 1 downto 0); 00235 RxDataK : out std_logic_vector((NO_OF_LANES * 2) - 1 downto 0); 00236 RxPolarity : in std_logic_vector(NO_OF_LANES - 1 downto 0); 00237 RxValid : out std_logic_vector(NO_OF_LANES - 1 downto 0); 00238 RxElecIdle : out std_logic_vector(NO_OF_LANES - 1 downto 0); 00239 RxStatus : out std_logic_vector((NO_OF_LANES * 3) - 1 downto 0); 00240 GTRefClkout : out std_logic_vector(NO_OF_LANES - 1 downto 0); 00241 plm_in_l0 : in std_logic; 00242 plm_in_rl : in std_logic; 00243 plm_in_dt : in std_logic; 00244 plm_in_rs : in std_logic; 00245 RxPLLLkDet : out std_logic_vector(NO_OF_LANES - 1 downto 0); 00246 TxDetectRx : in std_logic; 00247 PhyStatus : out std_logic_vector(NO_OF_LANES - 1 downto 0); 00248 TXPdownAsynch : in std_logic; 00249 PowerDown : in std_logic_vector((NO_OF_LANES * 2) - 1 downto 0); 00250 Rate : in std_logic; 00251 Reset_n : in std_logic; 00252 GTReset_n : in std_logic; 00253 PCLK : in std_logic; 00254 REFCLK : in std_logic; 00255 TxDeemph : in std_logic; 00256 TxMargin : in std_logic; 00257 TxSwing : in std_logic; 00258 ChanIsAligned : out std_logic_vector(NO_OF_LANES - 1 downto 0); 00259 local_pcs_reset : in std_logic; 00260 RxResetDone : out std_logic; 00261 SyncDone : out std_logic; 00262 DRPCLK : in std_logic; 00263 TxOutClk : out std_logic 00264 ); 00265 end component; 00266 00267 constant TCQ : integer := 1; -- clock to out delay model 00268 00269 FUNCTION to_stdlogic ( 00270 in_val : IN boolean) RETURN std_logic IS 00271 BEGIN 00272 IF (in_val) THEN 00273 RETURN('1'); 00274 ELSE 00275 RETURN('0'); 00276 END IF; 00277 END to_stdlogic; 00278 00279 FUNCTION and_bw ( 00280 val_in : std_logic_vector) RETURN std_logic IS 00281 00282 VARIABLE ret : std_logic := '1'; 00283 BEGIN 00284 FOR index IN val_in'RANGE LOOP 00285 ret := ret AND val_in(index); 00286 END LOOP; 00287 RETURN(ret); 00288 END and_bw; 00289 00290 FUNCTION nand_bw ( 00291 val_in : std_logic_vector) RETURN std_logic IS 00292 00293 VARIABLE ret : std_logic := '1'; 00294 BEGIN 00295 FOR index IN val_in'RANGE LOOP 00296 ret := ret AND val_in(index); 00297 END LOOP; 00298 RETURN(NOT ret); 00299 END nand_bw; 00300 00301 signal gt_rx_phy_status_wire : std_logic_vector(7 downto 0); 00302 signal gt_rxchanisaligned_wire : std_logic_vector(7 downto 0); 00303 signal gt_rx_data_k_wire : std_logic_vector(127 downto 0); 00304 signal gt_rx_data_wire : std_logic_vector(127 downto 0); 00305 signal gt_rx_elec_idle_wire : std_logic_vector(7 downto 0); 00306 signal gt_rx_status_wire : std_logic_vector(23 downto 0); 00307 signal gt_rx_valid_wire : std_logic_vector(7 downto 0); 00308 signal gt_rx_polarity : std_logic_vector(7 downto 0); 00309 signal gt_power_down : std_logic_vector(15 downto 0); 00310 signal gt_tx_char_disp_mode : std_logic_vector(7 downto 0); 00311 signal gt_tx_data_k : std_logic_vector(15 downto 0); 00312 signal gt_tx_data : std_logic_vector(127 downto 0); 00313 signal gt_tx_detect_rx_loopback : std_logic; 00314 signal gt_tx_elec_idle : std_logic_vector(7 downto 0); 00315 signal gt_rx_elec_idle_reset : std_logic_vector(7 downto 0); 00316 00317 signal plllkdet : std_logic_vector(NO_OF_LANES - 1 downto 0); 00318 signal RxResetDone : std_logic; 00319 signal plm_in_l0 : std_logic; 00320 signal plm_in_rl : std_logic; 00321 signal plm_in_dt : std_logic; 00322 signal plm_in_rs : std_logic; 00323 00324 signal local_pcs_reset : std_logic; 00325 signal local_pcs_reset_done : std_logic; 00326 signal cnt_local_pcs_reset : std_logic_vector(3 downto 0); 00327 signal phy_rdy_pre_cnt : std_logic_vector(4 downto 0); 00328 signal pl_ltssm_state_q : std_logic_vector(5 downto 0); 00329 00330 signal SyncDone : std_logic; 00331 00332 -- X-HDL generated signals 00333 00334 signal v6pcie5 : std_logic; 00335 00336 -- Declare intermediate signals for referenced outputs 00337 signal pci_exp_txn_v6pcie2 : std_logic_vector((NO_OF_LANES - 1) downto 0); 00338 signal pci_exp_txp_v6pcie3 : std_logic_vector((NO_OF_LANES - 1) downto 0); 00339 signal gt_pll_lock_v6pcie1 : std_logic; 00340 signal phy_rdy_n_v6pcie4 : std_logic; 00341 signal TxOutClk_v6pcie0 : std_logic; 00342 00343 signal plllkdet_nand : std_logic; 00344 00345 begin 00346 -- Drive referenced outputs 00347 pci_exp_txn <= pci_exp_txn_v6pcie2; 00348 pci_exp_txp <= pci_exp_txp_v6pcie3; 00349 gt_pll_lock <= gt_pll_lock_v6pcie1; 00350 phy_rdy_n <= phy_rdy_n_v6pcie4; 00351 TxOutClk <= TxOutClk_v6pcie0; 00352 plm_in_l0 <= to_stdlogic((pl_ltssm_state = "010110")); 00353 plm_in_rl <= to_stdlogic((pl_ltssm_state = "011100")); 00354 plm_in_dt <= to_stdlogic((pl_ltssm_state = "101101")); 00355 plm_in_rs <= to_stdlogic((pl_ltssm_state = "011111")); 00356 00357 v6pcie5 <= not(clock_locked); 00358 00359 gtx_v6_i : gtx_wrapper_v6 00360 generic map ( 00361 NO_OF_LANES => NO_OF_LANES, 00362 REF_CLK_FREQ => REF_CLK_FREQ, 00363 PL_FAST_TRAIN => PL_FAST_TRAIN 00364 ) 00365 port map ( 00366 00367 -- TX 00368 TX => pci_exp_txp_v6pcie3 (((NO_OF_LANES) - 1) downto 0), 00369 TXN => pci_exp_txn_v6pcie2 (((NO_OF_LANES) - 1) downto 0), 00370 TxData => gt_tx_data(((16 * NO_OF_LANES) - 1) downto 0), 00371 TxDataK => gt_tx_data_k(((2 * NO_OF_LANES) - 1) downto 0), 00372 TxElecIdle => gt_tx_elec_idle (((NO_OF_LANES) - 1) downto 0), 00373 TxCompliance => gt_tx_char_disp_mode (((NO_OF_LANES) - 1) downto 0), 00374 00375 -- RX 00376 RX => pci_exp_rxp(((NO_OF_LANES) - 1) downto 0), 00377 RXN => pci_exp_rxn(((NO_OF_LANES) - 1) downto 0), 00378 RxData => gt_rx_data_wire (((16 * NO_OF_LANES) - 1) downto 0), 00379 RxDataK => gt_rx_data_k_wire (((2 * NO_OF_LANES) - 1) downto 0), 00380 RxPolarity => gt_rx_polarity(((NO_OF_LANES) - 1) downto 0), 00381 RxValid => gt_rx_valid_wire (((NO_OF_LANES) - 1) downto 0), 00382 RxElecIdle => gt_rx_elec_idle_wire (((NO_OF_LANES) - 1) downto 0), 00383 RxStatus => gt_rx_status_wire (((3 * NO_OF_LANES) - 1) downto 0), 00384 00385 -- other 00386 GTRefClkout => open, 00387 plm_in_l0 => plm_in_l0, 00388 plm_in_rl => plm_in_rl, 00389 plm_in_dt => plm_in_dt, 00390 plm_in_rs => plm_in_rs, 00391 RxPLLLkDet => plllkdet, 00392 ChanIsAligned => gt_rxchanisaligned_wire(((NO_OF_LANES) - 1) downto 0), 00393 TxDetectRx => gt_tx_detect_rx_loopback, 00394 PhyStatus => gt_rx_phy_status_wire(((NO_OF_LANES) - 1) downto 0), 00395 TXPdownAsynch => v6pcie5, 00396 PowerDown => gt_power_down(((2 * NO_OF_LANES) - 1) downto 0), 00397 Rate => pipe_tx_rate, 00398 Reset_n => clock_locked, 00399 GTReset_n => sys_rst_n, 00400 PCLK => pipe_clk, 00401 REFCLK => sys_clk, 00402 DRPCLK => drp_clk, 00403 TxDeemph => pipe_tx_deemph, 00404 TxMargin => pipe_tx_margin(2), 00405 TxSwing => pipe_tx_swing, 00406 local_pcs_reset => local_pcs_reset, 00407 RxResetDone => RxResetDone, 00408 SyncDone => SyncDone, 00409 TxOutClk => TxOutClk_v6pcie0 00410 ); 00411 00412 pipe_rx0_phy_status <= gt_rx_phy_status_wire(0); 00413 pipe_rx1_phy_status <= gt_rx_phy_status_wire(1) when (NO_OF_LANES >= 2) else 00414 '0'; 00415 pipe_rx2_phy_status <= gt_rx_phy_status_wire(2) when (NO_OF_LANES >= 4) else 00416 '0'; 00417 pipe_rx3_phy_status <= gt_rx_phy_status_wire(3) when (NO_OF_LANES >= 4) else 00418 '0'; 00419 pipe_rx4_phy_status <= gt_rx_phy_status_wire(4) when (NO_OF_LANES >= 8) else 00420 '0'; 00421 pipe_rx5_phy_status <= gt_rx_phy_status_wire(5) when (NO_OF_LANES >= 8) else 00422 '0'; 00423 pipe_rx6_phy_status <= gt_rx_phy_status_wire(6) when (NO_OF_LANES >= 8) else 00424 '0'; 00425 pipe_rx7_phy_status <= gt_rx_phy_status_wire(7) when (NO_OF_LANES >= 8) else 00426 '0'; 00427 00428 pipe_rx0_chanisaligned <= gt_rxchanisaligned_wire(0); 00429 pipe_rx1_chanisaligned <= gt_rxchanisaligned_wire(1) when (NO_OF_LANES >= 2) else 00430 '0'; 00431 pipe_rx2_chanisaligned <= gt_rxchanisaligned_wire(2) when (NO_OF_LANES >= 4) else 00432 '0'; 00433 pipe_rx3_chanisaligned <= gt_rxchanisaligned_wire(3) when (NO_OF_LANES >= 4) else 00434 '0'; 00435 pipe_rx4_chanisaligned <= gt_rxchanisaligned_wire(4) when (NO_OF_LANES >= 8) else 00436 '0'; 00437 pipe_rx5_chanisaligned <= gt_rxchanisaligned_wire(5) when (NO_OF_LANES >= 8) else 00438 '0'; 00439 pipe_rx6_chanisaligned <= gt_rxchanisaligned_wire(6) when (NO_OF_LANES >= 8) else 00440 '0'; 00441 pipe_rx7_chanisaligned <= gt_rxchanisaligned_wire(7) when (NO_OF_LANES >= 8) else 00442 '0'; 00443 00444 --<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< 00445 --<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< 00446 00447 pipe_rx0_char_is_k <= (gt_rx_data_k_wire(1) & gt_rx_data_k_wire(0)); 00448 pipe_rx1_char_is_k <= (gt_rx_data_k_wire(3) & gt_rx_data_k_wire(2)) when (NO_OF_LANES >= 2) else 00449 "00"; 00450 pipe_rx2_char_is_k <= (gt_rx_data_k_wire(5) & gt_rx_data_k_wire(4)) when (NO_OF_LANES >= 4) else 00451 "00"; 00452 pipe_rx3_char_is_k <= (gt_rx_data_k_wire(7) & gt_rx_data_k_wire(6)) when (NO_OF_LANES >= 4) else 00453 "00"; 00454 pipe_rx4_char_is_k <= (gt_rx_data_k_wire(9) & gt_rx_data_k_wire(8)) when (NO_OF_LANES >= 8) else 00455 "00"; 00456 pipe_rx5_char_is_k <= (gt_rx_data_k_wire(11) & gt_rx_data_k_wire(10)) when (NO_OF_LANES >= 8) else 00457 "00"; 00458 pipe_rx6_char_is_k <= (gt_rx_data_k_wire(13) & gt_rx_data_k_wire(12)) when (NO_OF_LANES >= 8) else 00459 "00"; 00460 pipe_rx7_char_is_k <= (gt_rx_data_k_wire(15) & gt_rx_data_k_wire(14)) when (NO_OF_LANES >= 8) else 00461 "00"; 00462 00463 pipe_rx0_data <= (gt_rx_data_wire(15 downto 8) & gt_rx_data_wire(7 downto 0)); 00464 pipe_rx1_data <= (gt_rx_data_wire(31 downto 24) & gt_rx_data_wire(23 downto 16)) when (NO_OF_LANES >= 2) else 00465 "0000000000000000"; 00466 pipe_rx2_data <= (gt_rx_data_wire(47 downto 40) & gt_rx_data_wire(39 downto 32)) when (NO_OF_LANES >= 4) else 00467 "0000000000000000"; 00468 pipe_rx3_data <= (gt_rx_data_wire(63 downto 56) & gt_rx_data_wire(55 downto 48)) when (NO_OF_LANES >= 4) else 00469 "0000000000000000"; 00470 pipe_rx4_data <= (gt_rx_data_wire(79 downto 72) & gt_rx_data_wire(71 downto 64)) when (NO_OF_LANES >= 8) else 00471 "0000000000000000"; 00472 pipe_rx5_data <= (gt_rx_data_wire(95 downto 88) & gt_rx_data_wire(87 downto 80)) when (NO_OF_LANES >= 8) else 00473 "0000000000000000"; 00474 pipe_rx6_data <= (gt_rx_data_wire(111 downto 104) & gt_rx_data_wire(103 downto 96)) when (NO_OF_LANES >= 8) else 00475 "0000000000000000"; 00476 pipe_rx7_data <= (gt_rx_data_wire(127 downto 120) & gt_rx_data_wire(119 downto 112)) when (NO_OF_LANES >= 8) else 00477 "0000000000000000"; 00478 00479 --<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< 00480 --<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< 00481 00482 pipe_rx0_elec_idle <= gt_rx_elec_idle_wire(0); 00483 pipe_rx1_elec_idle <= gt_rx_elec_idle_wire(1) when (NO_OF_LANES >= 2) else 00484 '1'; 00485 pipe_rx2_elec_idle <= gt_rx_elec_idle_wire(2) when (NO_OF_LANES >= 4) else 00486 '1'; 00487 pipe_rx3_elec_idle <= gt_rx_elec_idle_wire(3) when (NO_OF_LANES >= 4) else 00488 '1'; 00489 pipe_rx4_elec_idle <= gt_rx_elec_idle_wire(4) when (NO_OF_LANES >= 8) else 00490 '1'; 00491 pipe_rx5_elec_idle <= gt_rx_elec_idle_wire(5) when (NO_OF_LANES >= 8) else 00492 '1'; 00493 pipe_rx6_elec_idle <= gt_rx_elec_idle_wire(6) when (NO_OF_LANES >= 8) else 00494 '1'; 00495 pipe_rx7_elec_idle <= gt_rx_elec_idle_wire(7) when (NO_OF_LANES >= 8) else 00496 '1'; 00497 00498 pipe_rx0_status <= gt_rx_status_wire(2 downto 0); 00499 pipe_rx1_status <= gt_rx_status_wire(5 downto 3) when (NO_OF_LANES >= 2) else 00500 "000"; 00501 pipe_rx2_status <= gt_rx_status_wire(8 downto 6) when (NO_OF_LANES >= 4) else 00502 "000"; 00503 pipe_rx3_status <= gt_rx_status_wire(11 downto 9) when (NO_OF_LANES >= 4) else 00504 "000"; 00505 pipe_rx4_status <= gt_rx_status_wire(14 downto 12) when (NO_OF_LANES >= 8) else 00506 "000"; 00507 pipe_rx5_status <= gt_rx_status_wire(17 downto 15) when (NO_OF_LANES >= 8) else 00508 "000"; 00509 pipe_rx6_status <= gt_rx_status_wire(20 downto 18) when (NO_OF_LANES >= 8) else 00510 "000"; 00511 pipe_rx7_status <= gt_rx_status_wire(23 downto 21) when (NO_OF_LANES >= 8) else 00512 "000"; 00513 00514 pipe_rx0_valid <= gt_rx_valid_wire(0); 00515 pipe_rx1_valid <= gt_rx_valid_wire(1) when (NO_OF_LANES >= 2) else 00516 '0'; 00517 pipe_rx2_valid <= gt_rx_valid_wire(2) when (NO_OF_LANES >= 4) else 00518 '0'; 00519 pipe_rx3_valid <= gt_rx_valid_wire(3) when (NO_OF_LANES >= 4) else 00520 '0'; 00521 pipe_rx4_valid <= gt_rx_valid_wire(4) when (NO_OF_LANES >= 8) else 00522 '0'; 00523 pipe_rx5_valid <= gt_rx_valid_wire(5) when (NO_OF_LANES >= 8) else 00524 '0'; 00525 pipe_rx6_valid <= gt_rx_valid_wire(6) when (NO_OF_LANES >= 8) else 00526 '0'; 00527 pipe_rx7_valid <= gt_rx_valid_wire(7) when (NO_OF_LANES >= 8) else 00528 '0'; 00529 00530 gt_rx_polarity(0) <= pipe_rx0_polarity; 00531 gt_rx_polarity(1) <= pipe_rx1_polarity; 00532 gt_rx_polarity(2) <= pipe_rx2_polarity; 00533 gt_rx_polarity(3) <= pipe_rx3_polarity; 00534 gt_rx_polarity(4) <= pipe_rx4_polarity; 00535 gt_rx_polarity(5) <= pipe_rx5_polarity; 00536 gt_rx_polarity(6) <= pipe_rx6_polarity; 00537 gt_rx_polarity(7) <= pipe_rx7_polarity; 00538 00539 gt_power_down(1 downto 0) <= pipe_tx0_powerdown; 00540 gt_power_down(3 downto 2) <= pipe_tx1_powerdown; 00541 gt_power_down(5 downto 4) <= pipe_tx2_powerdown; 00542 gt_power_down(7 downto 6) <= pipe_tx3_powerdown; 00543 gt_power_down(9 downto 8) <= pipe_tx4_powerdown; 00544 gt_power_down(11 downto 10) <= pipe_tx5_powerdown; 00545 gt_power_down(13 downto 12) <= pipe_tx6_powerdown; 00546 gt_power_down(15 downto 14) <= pipe_tx7_powerdown; 00547 00548 gt_tx_char_disp_mode <= (pipe_tx7_compliance & pipe_tx6_compliance & pipe_tx5_compliance & pipe_tx4_compliance & pipe_tx3_compliance & pipe_tx2_compliance & pipe_tx1_compliance & pipe_tx0_compliance); 00549 00550 gt_tx_data_k <= (pipe_tx7_char_is_k & pipe_tx6_char_is_k & pipe_tx5_char_is_k & pipe_tx4_char_is_k & pipe_tx3_char_is_k & pipe_tx2_char_is_k & pipe_tx1_char_is_k & pipe_tx0_char_is_k); 00551 00552 gt_tx_data <= (pipe_tx7_data & pipe_tx6_data & pipe_tx5_data & pipe_tx4_data & pipe_tx3_data & pipe_tx2_data & pipe_tx1_data & pipe_tx0_data); 00553 00554 gt_tx_detect_rx_loopback <= pipe_tx_rcvr_det; 00555 00556 gt_tx_elec_idle <= (pipe_tx7_elec_idle & pipe_tx6_elec_idle & pipe_tx5_elec_idle & pipe_tx4_elec_idle & pipe_tx3_elec_idle & pipe_tx2_elec_idle & pipe_tx1_elec_idle & pipe_tx0_elec_idle); 00557 00558 gt_pll_lock_v6pcie1 <= and_bw(plllkdet(NO_OF_LANES - 1 downto 0)) or not(phy_rdy_pre_cnt(4)); 00559 00560 plllkdet_nand <= nand_bw(plllkdet(NO_OF_LANES - 1 downto 0)); 00561 00562 -- Asserted after all workarounds have completed. 00563 00564 process (pipe_clk, clock_locked) 00565 begin 00566 00567 if ((not(clock_locked)) = '1') then 00568 00569 phy_rdy_n_v6pcie4 <= '1' after (TCQ)*1 ps; 00570 00571 elsif (pipe_clk'event and pipe_clk = '1') then 00572 00573 if (plllkdet_nand = '1') then 00574 phy_rdy_n_v6pcie4 <= '1' after (TCQ)*1 ps; 00575 elsif ((local_pcs_reset_done and RxResetDone and phy_rdy_n_v6pcie4 and SyncDone) = '1') then 00576 phy_rdy_n_v6pcie4 <= '0' after (TCQ)*1 ps; 00577 end if; 00578 00579 end if; 00580 end process; 00581 00582 00583 -- Handle the warm reset case, where sys_rst_n is asseted when 00584 -- phy_rdy_n is asserted. phy_rdy_n is to be de-asserted 00585 -- before gt_pll_lock is de-asserted so that synnchronous 00586 -- logic see reset de-asset before clock is lost. 00587 00588 process (pipe_clk, clock_locked) 00589 begin 00590 00591 if ((not(clock_locked)) = '1') then 00592 00593 phy_rdy_pre_cnt <= "11111" after (TCQ)*1 ps; 00594 00595 elsif (pipe_clk'event and pipe_clk = '1') then 00596 00597 if ((gt_pll_lock_v6pcie1 and phy_rdy_n_v6pcie4) = '1') then 00598 00599 phy_rdy_pre_cnt <= phy_rdy_pre_cnt + "00001" after (TCQ)*1 ps; 00600 00601 end if; 00602 end if; 00603 end process; 00604 00605 00606 process (pipe_clk, clock_locked) 00607 begin 00608 00609 if ((not(clock_locked)) = '1') then 00610 00611 cnt_local_pcs_reset <= "1111" after (TCQ)*1 ps; 00612 local_pcs_reset <= '0' after (TCQ)*1 ps; 00613 local_pcs_reset_done <= '0' after (TCQ)*1 ps; 00614 00615 elsif (pipe_clk'event and pipe_clk = '1') then 00616 00617 if ((local_pcs_reset = '0') and (cnt_local_pcs_reset = "1111")) then 00618 local_pcs_reset <= '1' after (TCQ)*1 ps; 00619 elsif ((local_pcs_reset = '1') and (cnt_local_pcs_reset /= "0000")) then 00620 local_pcs_reset <= '1' after (TCQ)*1 ps; 00621 cnt_local_pcs_reset <= cnt_local_pcs_reset - "0001" after (TCQ)*1 ps; 00622 elsif ((local_pcs_reset = '1') and (cnt_local_pcs_reset = "0000")) then 00623 local_pcs_reset <= '0' after (TCQ)*1 ps; 00624 local_pcs_reset_done <= '1' after (TCQ)*1 ps; 00625 end if; 00626 00627 end if; 00628 end process; 00629 00630 process (pipe_clk, clock_locked) 00631 begin 00632 00633 if ((not(clock_locked)) = '1') then 00634 00635 pl_ltssm_state_q <= "000000" after (TCQ)*1 ps; 00636 00637 elsif (pipe_clk'event and pipe_clk = '1') then 00638 00639 pl_ltssm_state_q <= pl_ltssm_state_q + "000001" after (TCQ)*1 ps; 00640 00641 end if; 00642 end process; 00643 00644 00645 end v6_pcie;
1.7.4