pcie_gtx_v6 Entity Reference

Граф наследования:pcie_gtx_v6:

Полный список членов класса

Architectures
v6_pcie	Architecture
Libraries
ieee
Packages
std_logic_1164
std_logic_unsigned
Generics
NO_OF_LANES	integer := 8
LINK_CAP_MAX_LINK_SPEED	bit_vector := x " 1 "
REF_CLK_FREQ	integer := 0
PL_FAST_TRAIN	boolean := false
Ports
pipe_tx_rcvr_det	in std_logic
pipe_tx_reset	in std_logic
pipe_tx_rate	in std_logic
pipe_tx_deemph	in std_logic
pipe_tx_margin	in std_logic_vector ( 2 downto 0 )
pipe_tx_swing	in std_logic
pipe_rx0_char_is_k	out std_logic_vector ( 1 downto 0 )
pipe_rx0_data	out std_logic_vector ( 15 downto 0 )
pipe_rx0_valid	out std_logic
pipe_rx0_chanisaligned	out std_logic
pipe_rx0_status	out std_logic_vector ( 2 downto 0 )
pipe_rx0_phy_status	out std_logic
pipe_rx0_elec_idle	out std_logic
pipe_rx0_polarity	in std_logic
pipe_tx0_compliance	in std_logic
pipe_tx0_char_is_k	in std_logic_vector ( 1 downto 0 )
pipe_tx0_data	in std_logic_vector ( 15 downto 0 )
pipe_tx0_elec_idle	in std_logic
pipe_tx0_powerdown	in std_logic_vector ( 1 downto 0 )
pipe_rx1_char_is_k	out std_logic_vector ( 1 downto 0 )
pipe_rx1_data	out std_logic_vector ( 15 downto 0 )
pipe_rx1_valid	out std_logic
pipe_rx1_chanisaligned	out std_logic
pipe_rx1_status	out std_logic_vector ( 2 downto 0 )
pipe_rx1_phy_status	out std_logic
pipe_rx1_elec_idle	out std_logic
pipe_rx1_polarity	in std_logic
pipe_tx1_compliance	in std_logic
pipe_tx1_char_is_k	in std_logic_vector ( 1 downto 0 )
pipe_tx1_data	in std_logic_vector ( 15 downto 0 )
pipe_tx1_elec_idle	in std_logic
pipe_tx1_powerdown	in std_logic_vector ( 1 downto 0 )
pipe_rx2_char_is_k	out std_logic_vector ( 1 downto 0 )
pipe_rx2_data	out std_logic_vector ( 15 downto 0 )
pipe_rx2_valid	out std_logic
pipe_rx2_chanisaligned	out std_logic
pipe_rx2_status	out std_logic_vector ( 2 downto 0 )
pipe_rx2_phy_status	out std_logic
pipe_rx2_elec_idle	out std_logic
pipe_rx2_polarity	in std_logic
pipe_tx2_compliance	in std_logic
pipe_tx2_char_is_k	in std_logic_vector ( 1 downto 0 )
pipe_tx2_data	in std_logic_vector ( 15 downto 0 )
pipe_tx2_elec_idle	in std_logic
pipe_tx2_powerdown	in std_logic_vector ( 1 downto 0 )
pipe_rx3_char_is_k	out std_logic_vector ( 1 downto 0 )
pipe_rx3_data	out std_logic_vector ( 15 downto 0 )
pipe_rx3_valid	out std_logic
pipe_rx3_chanisaligned	out std_logic
pipe_rx3_status	out std_logic_vector ( 2 downto 0 )
pipe_rx3_phy_status	out std_logic
pipe_rx3_elec_idle	out std_logic
pipe_rx3_polarity	in std_logic
pipe_tx3_compliance	in std_logic
pipe_tx3_char_is_k	in std_logic_vector ( 1 downto 0 )
pipe_tx3_data	in std_logic_vector ( 15 downto 0 )
pipe_tx3_elec_idle	in std_logic
pipe_tx3_powerdown	in std_logic_vector ( 1 downto 0 )
pipe_rx4_char_is_k	out std_logic_vector ( 1 downto 0 )
pipe_rx4_data	out std_logic_vector ( 15 downto 0 )
pipe_rx4_valid	out std_logic
pipe_rx4_chanisaligned	out std_logic
pipe_rx4_status	out std_logic_vector ( 2 downto 0 )
pipe_rx4_phy_status	out std_logic
pipe_rx4_elec_idle	out std_logic
pipe_rx4_polarity	in std_logic
pipe_tx4_compliance	in std_logic
pipe_tx4_char_is_k	in std_logic_vector ( 1 downto 0 )
pipe_tx4_data	in std_logic_vector ( 15 downto 0 )
pipe_tx4_elec_idle	in std_logic
pipe_tx4_powerdown	in std_logic_vector ( 1 downto 0 )
pipe_rx5_char_is_k	out std_logic_vector ( 1 downto 0 )
pipe_rx5_data	out std_logic_vector ( 15 downto 0 )
pipe_rx5_valid	out std_logic
pipe_rx5_chanisaligned	out std_logic
pipe_rx5_status	out std_logic_vector ( 2 downto 0 )
pipe_rx5_phy_status	out std_logic
pipe_rx5_elec_idle	out std_logic
pipe_rx5_polarity	in std_logic
pipe_tx5_compliance	in std_logic
pipe_tx5_char_is_k	in std_logic_vector ( 1 downto 0 )
pipe_tx5_data	in std_logic_vector ( 15 downto 0 )
pipe_tx5_elec_idle	in std_logic
pipe_tx5_powerdown	in std_logic_vector ( 1 downto 0 )
pipe_rx6_char_is_k	out std_logic_vector ( 1 downto 0 )
pipe_rx6_data	out std_logic_vector ( 15 downto 0 )
pipe_rx6_valid	out std_logic
pipe_rx6_chanisaligned	out std_logic
pipe_rx6_status	out std_logic_vector ( 2 downto 0 )
pipe_rx6_phy_status	out std_logic
pipe_rx6_elec_idle	out std_logic
pipe_rx6_polarity	in std_logic
pipe_tx6_compliance	in std_logic
pipe_tx6_char_is_k	in std_logic_vector ( 1 downto 0 )
pipe_tx6_data	in std_logic_vector ( 15 downto 0 )
pipe_tx6_elec_idle	in std_logic
pipe_tx6_powerdown	in std_logic_vector ( 1 downto 0 )
pipe_rx7_char_is_k	out std_logic_vector ( 1 downto 0 )
pipe_rx7_data	out std_logic_vector ( 15 downto 0 )
pipe_rx7_valid	out std_logic
pipe_rx7_chanisaligned	out std_logic
pipe_rx7_status	out std_logic_vector ( 2 downto 0 )
pipe_rx7_phy_status	out std_logic
pipe_rx7_elec_idle	out std_logic
pipe_rx7_polarity	in std_logic
pipe_tx7_compliance	in std_logic
pipe_tx7_char_is_k	in std_logic_vector ( 1 downto 0 )
pipe_tx7_data	in std_logic_vector ( 15 downto 0 )
pipe_tx7_elec_idle	in std_logic
pipe_tx7_powerdown	in std_logic_vector ( 1 downto 0 )
pci_exp_txn	out std_logic_vector ( ( no_of_lanes- 1 ) downto 0 )
pci_exp_txp	out std_logic_vector ( ( no_of_lanes- 1 ) downto 0 )
pci_exp_rxn	in std_logic_vector ( ( no_of_lanes- 1 ) downto 0 )
pci_exp_rxp	in std_logic_vector ( ( no_of_lanes- 1 ) downto 0 )
sys_clk	in std_logic
sys_rst_n	in std_logic
pipe_clk	in std_logic
drp_clk	in std_logic
clock_locked	in std_logic
gt_pll_lock	out std_logic
pl_ltssm_state	in std_logic_vector ( 5 downto 0 )
phy_rdy_n	out std_logic
TxOutClk	out std_logic

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Подробное описание

См. определение в файле pcie_gtx_v6.vhd строка 63

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Объявления и описания членов класса находятся в файле:

• pcie_src/pcie_core64_m1/source_virtex6/pcie_gtx_v6.vhd