Граф наследования:gtx_wrapper_v6:
Architectures | |
| v6_pcie | Architecture |
Libraries | |
| ieee | |
| unisim | |
Packages | |
| std_logic_1164 | |
| std_logic_unsigned | |
| vcomponents | |
Generics | |
| NO_OF_LANES | integer := 1 |
| REF_CLK_FREQ | integer := 0 |
| PL_FAST_TRAIN | boolean := false |
Ports | |
| TX | out std_logic_vector ( no_of_lanes- 1 downto 0 ) |
| TXN | out std_logic_vector ( no_of_lanes- 1 downto 0 ) |
| TxData | in std_logic_vector ( ( no_of_lanes * 16 ) - 1 downto 0 ) |
| TxDataK | in std_logic_vector ( ( no_of_lanes * 2 ) - 1 downto 0 ) |
| TxElecIdle | in std_logic_vector ( no_of_lanes- 1 downto 0 ) |
| TxCompliance | in std_logic_vector ( no_of_lanes- 1 downto 0 ) |
| RX | in std_logic_vector ( no_of_lanes- 1 downto 0 ) |
| RXN | in std_logic_vector ( no_of_lanes- 1 downto 0 ) |
| RxData | out std_logic_vector ( ( no_of_lanes * 16 ) - 1 downto 0 ) |
| RxDataK | out std_logic_vector ( ( no_of_lanes * 2 ) - 1 downto 0 ) |
| RxPolarity | in std_logic_vector ( no_of_lanes- 1 downto 0 ) |
| RxValid | out std_logic_vector ( no_of_lanes- 1 downto 0 ) |
| RxElecIdle | out std_logic_vector ( no_of_lanes- 1 downto 0 ) |
| RxStatus | out std_logic_vector ( ( no_of_lanes * 3 ) - 1 downto 0 ) |
| GTRefClkout | out std_logic_vector ( no_of_lanes- 1 downto 0 ) |
| plm_in_l0 | in std_logic |
| plm_in_rl | in std_logic |
| plm_in_dt | in std_logic |
| plm_in_rs | in std_logic |
| RxPLLLkDet | out std_logic_vector ( no_of_lanes- 1 downto 0 ) |
| TxDetectRx | in std_logic |
| PhyStatus | out std_logic_vector ( no_of_lanes- 1 downto 0 ) |
| TXPdownAsynch | in std_logic |
| PowerDown | in std_logic_vector ( ( no_of_lanes * 2 ) - 1 downto 0 ) |
| Rate | in std_logic |
| Reset_n | in std_logic |
| GTReset_n | in std_logic |
| PCLK | in std_logic |
| REFCLK | in std_logic |
| TxDeemph | in std_logic |
| TxMargin | in std_logic |
| TxSwing | in std_logic |
| ChanIsAligned | out std_logic_vector ( no_of_lanes- 1 downto 0 ) |
| local_pcs_reset | in std_logic |
| RxResetDone | out std_logic |
| SyncDone | out std_logic |
| DRPCLK | in std_logic |
| TxOutClk | out std_logic |
Подробное описание
См. определение в файле gtx_wrapper_v6.vhd строка 66
Объявления и описания членов класса находятся в файле:
- pcie_src/pcie_core64_m1/source_virtex6/gtx_wrapper_v6.vhd
