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DS_DMA
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00001 ------------------------------------------------------------------------------- 00002 -- 00003 -- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved. 00004 -- 00005 -- This file contains confidential and proprietary information 00006 -- of Xilinx, Inc. and is protected under U.S. and 00007 -- international copyright and other intellectual property 00008 -- laws. 00009 -- 00010 -- DISCLAIMER 00011 -- This disclaimer is not a license and does not grant any 00012 -- rights to the materials distributed herewith. Except as 00013 -- otherwise provided in a valid license issued to you by 00014 -- Xilinx, and to the maximum extent permitted by applicable 00015 -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 00016 -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 00017 -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 00018 -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 00019 -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 00020 -- (2) Xilinx shall not be liable (whether in contract or tort, 00021 -- including negligence, or under any other theory of 00022 -- liability) for any loss or damage of any kind or nature 00023 -- related to, arising under or in connection with these 00024 -- materials, including for any direct, or any indirect, 00025 -- special, incidental, or consequential loss or damage 00026 -- (including loss of data, profits, goodwill, or any type of 00027 -- loss or damage suffered as a result of any action brought 00028 -- by a third party) even if such damage or loss was 00029 -- reasonably foreseeable or Xilinx had been advised of the 00030 -- possibility of the same. 00031 -- 00032 -- CRITICAL APPLICATIONS 00033 -- Xilinx products are not designed or intended to be fail- 00034 -- safe, or for use in any application requiring fail-safe 00035 -- performance, such as life-support or safety devices or 00036 -- systems, Class III medical devices, nuclear facilities, 00037 -- applications related to the deployment of airbags, or any 00038 -- other applications that could lead to death, personal 00039 -- injury, or severe property or environmental damage 00040 -- (individually and collectively, "Critical 00041 -- Applications"). Customer assumes the sole risk and 00042 -- liability of any use of Xilinx products in Critical 00043 -- Applications, subject only to applicable laws and 00044 -- regulations governing limitations on product liability. 00045 -- 00046 -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 00047 -- PART OF THIS FILE AT ALL TIMES. 00048 -- 00049 ------------------------------------------------------------------------------- 00050 -- Project : Virtex-6 Integrated Block for PCI Express 00051 -- File : gtx_wrapper_v6.vhd 00052 -- Version : 2.3 00053 -- Description: GTX module for Virtex6 PCIe Block 00054 -- 00055 -- 00056 -- 00057 -------------------------------------------------------------------------------- 00058 00059 library ieee; 00060 use ieee.std_logic_1164.all; 00061 use ieee.std_logic_unsigned.all; 00062 00063 library unisim; 00064 use unisim.vcomponents.all; 00065 00066 entity gtx_wrapper_v6 is 00067 generic ( 00068 NO_OF_LANES : integer := 1; 00069 REF_CLK_FREQ : integer := 0; 00070 PL_FAST_TRAIN : boolean := FALSE 00071 ); 00072 port ( 00073 00074 -- TX 00075 TX : out std_logic_vector(NO_OF_LANES - 1 downto 0); 00076 TXN : out std_logic_vector(NO_OF_LANES - 1 downto 0); 00077 TxData : in std_logic_vector((NO_OF_LANES * 16) - 1 downto 0); 00078 TxDataK : in std_logic_vector((NO_OF_LANES * 2) - 1 downto 0); 00079 TxElecIdle : in std_logic_vector(NO_OF_LANES - 1 downto 0); 00080 TxCompliance : in std_logic_vector(NO_OF_LANES - 1 downto 0); 00081 00082 -- RX 00083 RX : in std_logic_vector(NO_OF_LANES - 1 downto 0); 00084 RXN : in std_logic_vector(NO_OF_LANES - 1 downto 0); 00085 RxData : out std_logic_vector((NO_OF_LANES * 16) - 1 downto 0); 00086 RxDataK : out std_logic_vector((NO_OF_LANES * 2) - 1 downto 0); 00087 RxPolarity : in std_logic_vector(NO_OF_LANES - 1 downto 0); 00088 RxValid : out std_logic_vector(NO_OF_LANES - 1 downto 0); 00089 RxElecIdle : out std_logic_vector(NO_OF_LANES - 1 downto 0); 00090 RxStatus : out std_logic_vector((NO_OF_LANES * 3) - 1 downto 0); 00091 00092 -- other 00093 GTRefClkout : out std_logic_vector(NO_OF_LANES - 1 downto 0); 00094 plm_in_l0 : in std_logic; 00095 plm_in_rl : in std_logic; 00096 plm_in_dt : in std_logic; 00097 plm_in_rs : in std_logic; 00098 RxPLLLkDet : out std_logic_vector(NO_OF_LANES - 1 downto 0); 00099 TxDetectRx : in std_logic; 00100 PhyStatus : out std_logic_vector(NO_OF_LANES - 1 downto 0); 00101 TXPdownAsynch : in std_logic; 00102 00103 PowerDown : in std_logic_vector((NO_OF_LANES * 2) - 1 downto 0); 00104 Rate : in std_logic; 00105 Reset_n : in std_logic; 00106 GTReset_n : in std_logic; 00107 PCLK : in std_logic; 00108 REFCLK : in std_logic; 00109 TxDeemph : in std_logic; 00110 TxMargin : in std_logic; 00111 TxSwing : in std_logic; 00112 ChanIsAligned : out std_logic_vector(NO_OF_LANES - 1 downto 0); 00113 local_pcs_reset : in std_logic; 00114 RxResetDone : out std_logic; 00115 SyncDone : out std_logic; 00116 DRPCLK : in std_logic; 00117 TxOutClk : out std_logic 00118 ); 00119 end gtx_wrapper_v6; 00120 00121 architecture v6_pcie of gtx_wrapper_v6 is 00122 component GTX_RX_VALID_FILTER_V6 is 00123 generic ( 00124 CLK_COR_MIN_LAT : integer 00125 ); 00126 port ( 00127 USER_RXCHARISK : out std_logic_vector(1 downto 0); 00128 USER_RXDATA : out std_logic_vector(15 downto 0); 00129 USER_RXVALID : out std_logic; 00130 USER_RXELECIDLE : out std_logic; 00131 USER_RX_STATUS : out std_logic_vector(2 downto 0); 00132 USER_RX_PHY_STATUS : out std_logic; 00133 GT_RXCHARISK : in std_logic_vector(1 downto 0); 00134 GT_RXDATA : in std_logic_vector(15 downto 0); 00135 GT_RXVALID : in std_logic; 00136 GT_RXELECIDLE : in std_logic; 00137 GT_RX_STATUS : in std_logic_vector(2 downto 0); 00138 GT_RX_PHY_STATUS : in std_logic; 00139 PLM_IN_L0 : in std_logic; 00140 PLM_IN_RS : in std_logic; 00141 USER_CLK : in std_logic; 00142 RESET : in std_logic 00143 ); 00144 end component; 00145 00146 component GTX_DRP_CHANALIGN_FIX_3752_V6 is 00147 generic ( 00148 C_SIMULATION : integer 00149 ); 00150 port ( 00151 dwe : out std_logic; 00152 din : out std_logic_vector(15 downto 0); 00153 den : out std_logic; 00154 daddr : out std_logic_vector(7 downto 0); 00155 drpstate : out std_logic_vector(3 downto 0); 00156 write_ts1 : in std_logic; 00157 write_fts : in std_logic; 00158 dout : in std_logic_vector(15 downto 0); 00159 drdy : in std_logic; 00160 Reset_n : in std_logic; 00161 drp_clk : in std_logic 00162 ); 00163 end component; 00164 00165 component GTX_TX_SYNC_RATE_V6 is 00166 generic ( 00167 C_SIMULATION : integer 00168 ); 00169 port ( 00170 ENPMAPHASEALIGN : out std_logic; 00171 PMASETPHASE : out std_logic; 00172 SYNC_DONE : out std_logic; 00173 OUT_DIV_RESET : out std_logic; 00174 PCS_RESET : out std_logic; 00175 USER_PHYSTATUS : out std_logic; 00176 TXALIGNDISABLE : out std_logic; 00177 DELAYALIGNRESET : out std_logic; 00178 USER_CLK : in std_logic; 00179 RESET : in std_logic; 00180 RATE : in std_logic; 00181 RATEDONE : in std_logic; 00182 GT_PHYSTATUS : in std_logic; 00183 RESETDONE : in std_logic 00184 ); 00185 end component; 00186 00187 FUNCTION to_stdlogicvector ( 00188 val_in : IN integer; 00189 length : IN integer) RETURN std_logic_vector IS 00190 00191 VARIABLE ret : std_logic_vector(length-1 DOWNTO 0) := (OTHERS => '0'); 00192 VARIABLE num : integer := val_in; 00193 VARIABLE x : integer; 00194 BEGIN 00195 FOR index IN 0 TO length-1 LOOP 00196 x := num rem 2; 00197 num := num/2; 00198 IF (x = 1) THEN 00199 ret(index) := '1'; 00200 ELSE 00201 ret(index) := '0'; 00202 END IF; 00203 END LOOP; 00204 RETURN(ret); 00205 END to_stdlogicvector; 00206 00207 FUNCTION and_bw ( 00208 val_in : std_logic_vector) RETURN std_logic IS 00209 00210 VARIABLE ret : std_logic := '1'; 00211 BEGIN 00212 FOR index IN val_in'RANGE LOOP 00213 ret := ret AND val_in(index); 00214 END LOOP; 00215 RETURN(ret); 00216 END and_bw; 00217 00218 FUNCTION to_integer ( 00219 in_val : IN boolean) RETURN integer IS 00220 BEGIN 00221 IF (in_val) THEN 00222 RETURN(1); 00223 ELSE 00224 RETURN(0); 00225 END IF; 00226 END to_integer; 00227 00228 FUNCTION to_stdlogic ( 00229 in_val : IN boolean) RETURN std_logic IS 00230 BEGIN 00231 IF (in_val) THEN 00232 RETURN('1'); 00233 ELSE 00234 RETURN('0'); 00235 END IF; 00236 END to_stdlogic; 00237 00238 -- purpose: PLL_CP_CFG selector function 00239 function pll_cp_cfg_sel ( 00240 ref_freq : integer) 00241 return bit_vector is 00242 begin -- pll_cp_cfg_sel 00243 if (ref_freq = 2) then 00244 return (X"05"); 00245 else 00246 return (X"05"); 00247 end if; 00248 end pll_cp_cfg_sel; 00249 00250 FUNCTION clk_div ( 00251 in_val : IN integer) RETURN integer IS 00252 BEGIN 00253 if (in_val = 0) THEN 00254 return (4); 00255 elsif (in_val = 1) then 00256 return (5); 00257 else 00258 return (10); 00259 end if; 00260 END clk_div; 00261 00262 FUNCTION pll_div ( 00263 in_val : IN integer) RETURN integer IS 00264 BEGIN 00265 if (in_val = 0) THEN 00266 return (5); 00267 elsif (in_val = 1) then 00268 return (4); 00269 elsif (in_val = 2) then 00270 return (2); 00271 else 00272 return (0); 00273 end if; 00274 END pll_div; 00275 00276 00277 -- ground and tied_to_vcc_i signals 00278 signal tied_to_ground_i : std_logic; 00279 signal tied_to_ground_vec_i : std_logic_vector(31 downto 0); 00280 signal tied_to_vcc_i : std_logic; 00281 00282 type type_v6pcie10 is array (NO_OF_LANES + 1 downto 0) of std_logic_vector(3 downto 0); 00283 type type_v6pcie11 is array (NO_OF_LANES - 1 downto 0) of std_logic; 00284 type type_v6pcie16 is array (NO_OF_LANES - 1 downto 0) of std_logic_vector(12 downto 0); 00285 00286 00287 -- dummy signals to avoid port mismatch with DUAL_GTX 00288 signal RxData_dummy : std_logic_vector(15 downto 0); 00289 signal RxDataK_dummy : std_logic_vector(1 downto 0); 00290 signal TxData_dummy : std_logic_vector(15 downto 0); 00291 signal TxDataK_dummy : std_logic_vector(1 downto 0); 00292 00293 -- inputs 00294 signal GTX_TxData : std_logic_vector((NO_OF_LANES * 16) - 1 downto 0); 00295 signal GTX_TxDataK : std_logic_vector((NO_OF_LANES * 2) - 1 downto 0); 00296 signal GTX_TxElecIdle : std_logic_vector((NO_OF_LANES) - 1 downto 0); 00297 signal GTX_TxCompliance : std_logic_vector((NO_OF_LANES - 1) downto 0); 00298 signal GTX_RXP : std_logic_vector((NO_OF_LANES) - 1 downto 0); 00299 signal GTX_RXN : std_logic_vector((NO_OF_LANES) - 1 downto 0); 00300 00301 -- outputs 00302 signal GTX_TXP : std_logic_vector((NO_OF_LANES) - 1 downto 0); 00303 signal GTX_TXN : std_logic_vector((NO_OF_LANES) - 1 downto 0); 00304 signal GTX_RxData : std_logic_vector((NO_OF_LANES * 16) - 1 downto 0); 00305 signal GTX_RxDataK : std_logic_vector((NO_OF_LANES * 2) - 1 downto 0); 00306 signal GTX_RxPolarity : std_logic_vector((NO_OF_LANES) - 1 downto 0); 00307 signal GTX_RxValid : std_logic_vector((NO_OF_LANES) - 1 downto 0); 00308 signal GTX_RxElecIdle : std_logic_vector((NO_OF_LANES) - 1 downto 0); 00309 signal GTX_RxResetDone : std_logic_vector((NO_OF_LANES - 1) downto 0); 00310 signal GTX_RxChbondLevel : std_logic_vector((NO_OF_LANES * 3) - 1 downto 0); 00311 signal GTX_RxStatus : std_logic_vector((NO_OF_LANES * 3) - 1 downto 0); 00312 00313 signal RXCHBOND : type_v6pcie10; 00314 signal TXBYPASS8B10B : std_logic_vector(3 downto 0); 00315 signal RXDEC8B10BUSE : std_logic; 00316 signal GTX_PhyStatus : std_logic_vector(NO_OF_LANES - 1 downto 0); 00317 signal RESETDONE : type_v6pcie11; 00318 signal GTXRESET : std_logic; 00319 signal RXRECCLK : std_logic; 00320 00321 signal SYNC_DONE : std_logic_vector(NO_OF_LANES - 1 downto 0); 00322 signal OUT_DIV_RESET : std_logic_vector(NO_OF_LANES - 1 downto 0); 00323 signal PCS_RESET : std_logic_vector(NO_OF_LANES - 1 downto 0); 00324 signal TXENPMAPHASEALIGN : std_logic_vector(NO_OF_LANES - 1 downto 0); 00325 signal TXPMASETPHASE : std_logic_vector(NO_OF_LANES - 1 downto 0); 00326 signal TXRESETDONE : std_logic_vector(NO_OF_LANES - 1 downto 0); 00327 signal TXRATEDONE : std_logic_vector(NO_OF_LANES - 1 downto 0); 00328 signal PHYSTATUS_int : std_logic_vector(NO_OF_LANES - 1 downto 0); 00329 signal RATE_CLK_SEL : std_logic_vector(NO_OF_LANES - 1 downto 0); 00330 signal TXOCLK : std_logic_vector(NO_OF_LANES - 1 downto 0); 00331 signal TXDLYALIGNDISABLE : std_logic_vector(NO_OF_LANES - 1 downto 0); 00332 signal TXDLYALIGNRESET : std_logic_vector(NO_OF_LANES - 1 downto 0); 00333 00334 signal GTX_RxResetDone_q : std_logic_vector((NO_OF_LANES - 1) downto 0); 00335 signal TXRESETDONE_q : std_logic_vector((NO_OF_LANES - 1) downto 0); 00336 00337 signal daddr : std_logic_vector((NO_OF_LANES * 8 - 1) downto 0); 00338 signal den : std_logic_vector(NO_OF_LANES - 1 downto 0); 00339 signal din : std_logic_vector((NO_OF_LANES * 16 - 1) downto 0); 00340 signal dwe : std_logic_vector(NO_OF_LANES - 1 downto 0); 00341 00342 signal drpstate : std_logic_vector((NO_OF_LANES * 4 - 1) downto 0); 00343 signal drdy : std_logic_vector(NO_OF_LANES - 1 downto 0); 00344 signal dout : std_logic_vector((NO_OF_LANES * 16 - 1) downto 0); 00345 00346 signal write_drp_cb_fts : std_logic; 00347 signal write_drp_cb_ts1 : std_logic; 00348 00349 -- X-HDL generated signals 00350 00351 signal v6pcie12 : std_logic; 00352 signal v6pcie13 : std_logic; 00353 signal v6pcie14 : std_logic_vector(NO_OF_LANES - 1 downto 0); 00354 signal v6pcie15 : std_logic; 00355 signal v6pcie16 : type_v6pcie16; 00356 signal v6pcie18 : std_logic_vector(1 downto 0); 00357 signal v6pcie21 : std_logic_vector((NO_OF_LANES*4) - 1 downto 0); 00358 signal v6pcie23 : std_logic_vector((NO_OF_LANES*32) - 1 downto 0); 00359 signal v6pcie24 : std_logic_vector(1 downto 0); 00360 signal v6pcie25 : std_logic_vector(NO_OF_LANES - 1 downto 0); 00361 signal v6pcie26 : std_logic_vector(19 downto 0); 00362 signal v6pcie27 : std_logic_vector((NO_OF_LANES * 4) - 1 downto 0); 00363 signal v6pcie28 : std_logic_vector((NO_OF_LANES * 4) - 1 downto 0); 00364 signal v6pcie29 : std_logic_vector((NO_OF_LANES * 32) - 1 downto 0) := (others => '0'); 00365 signal v6pcie30 : std_logic_vector(2 downto 0); 00366 00367 -- Declare intermediate signals for referenced outputs 00368 signal RxData_v6pcie3 : std_logic_vector((NO_OF_LANES * 16) - 1 downto 0); 00369 signal RxDataK_v6pcie4 : std_logic_vector((NO_OF_LANES * 2) - 1 downto 0); 00370 signal RxValid_v6pcie8 : std_logic_vector(NO_OF_LANES - 1 downto 0); 00371 signal RxElecIdle_v6pcie5 : std_logic_vector(NO_OF_LANES - 1 downto 0); 00372 signal RxStatus_v6pcie7 : std_logic_vector((NO_OF_LANES * 3) - 1 downto 0); 00373 signal RxPLLLkDet_v6pcie6 : std_logic_vector(NO_OF_LANES - 1 downto 0); 00374 signal PhyStatus_v6pcie1 : std_logic_vector(NO_OF_LANES - 1 downto 0); 00375 signal ChanIsAligned_v6pcie0 : std_logic_vector(NO_OF_LANES - 1 downto 0); 00376 begin 00377 00378 --------------------------- Static signal Assignments --------------------- 00379 00380 tied_to_ground_i <= '0'; 00381 tied_to_ground_vec_i(31 downto 0) <= (others => '0'); 00382 tied_to_vcc_i <= '1'; 00383 00384 -- Drive referenced outputs 00385 RxData <= RxData_v6pcie3; 00386 RxDataK <= RxDataK_v6pcie4; 00387 RxValid <= RxValid_v6pcie8; 00388 RxElecIdle <= RxElecIdle_v6pcie5; 00389 RxStatus <= RxStatus_v6pcie7; 00390 RxPLLLkDet <= RxPLLLkDet_v6pcie6; 00391 PhyStatus <= PhyStatus_v6pcie1; 00392 ChanIsAligned <= ChanIsAligned_v6pcie0; 00393 GTX_TxData <= TxData; 00394 GTX_TxDataK <= TxDataK; 00395 GTX_TxElecIdle <= TxElecIdle; 00396 GTX_TxCompliance <= TxCompliance; 00397 GTX_RXP <= RX((NO_OF_LANES) - 1 downto 0); 00398 GTX_RXN <= RXN((NO_OF_LANES) - 1 downto 0); 00399 GTX_RxPolarity <= RxPolarity; 00400 TXBYPASS8B10B <= "0000"; 00401 RXDEC8B10BUSE <= '1'; 00402 GTXRESET <= '0'; 00403 00404 RxResetDone <= and_bw((GTX_RxResetDone_q((NO_OF_LANES) - 1 downto 0))); 00405 TX((NO_OF_LANES - 1) downto 0) <= GTX_TXP((NO_OF_LANES - 1) downto 0); 00406 TXN((NO_OF_LANES - 1) downto 0) <= GTX_TXN((NO_OF_LANES - 1) downto 0); 00407 RXCHBOND(0) <= "0000"; 00408 TxData_dummy <= "0000000000000000"; 00409 TxDataK_dummy <= "00"; 00410 SyncDone <= and_bw((SYNC_DONE((NO_OF_LANES - 1) downto 0))); 00411 TxOutClk <= TXOCLK(0); 00412 00413 write_drp_cb_fts <= plm_in_l0; 00414 write_drp_cb_ts1 <= plm_in_rl or plm_in_dt; 00415 00416 00417 -- pipeline to improve timing 00418 process (PCLK) 00419 begin 00420 if (PCLK'event and PCLK = '1') then 00421 00422 GTX_RxResetDone_q((NO_OF_LANES - 1) downto 0) <= GTX_RxResetDone((NO_OF_LANES - 1) downto 0); 00423 00424 TXRESETDONE_q((NO_OF_LANES - 1) downto 0) <= TXRESETDONE((NO_OF_LANES - 1) downto 0); 00425 end if; 00426 end process; 00427 00428 GTXD : for i in 0 to (NO_OF_LANES - 1) generate 00429 GTX_RxChbondLevel((3 * i) + 2 downto (3 * i)) <= (to_stdlogicvector((NO_OF_LANES - (i + 1)), 3)); 00430 00431 GTX_DRP_CHANALIGN_FIX_3752 : GTX_DRP_CHANALIGN_FIX_3752_V6 00432 generic map ( 00433 C_SIMULATION => to_integer(PL_FAST_TRAIN) 00434 ) 00435 port map ( 00436 00437 dwe => dwe(i), 00438 din => din((16 * i) + 15 downto (16 * i)), 00439 den => den(i), 00440 daddr => daddr((8 * i) + 7 downto (8 * i)), 00441 drpstate => drpstate((4 * i) + 3 downto (4 * i)), 00442 write_ts1 => write_drp_cb_ts1, 00443 write_fts => write_drp_cb_fts, 00444 dout => dout((16 * i) + 15 downto (16 * i)), 00445 drdy => drdy(i), 00446 Reset_n => Reset_n, 00447 drp_clk => DRPCLK 00448 ); 00449 00450 v6pcie12 <= not(Reset_n); --I 00451 00452 GTX_RX_VALID_FILTER : GTX_RX_VALID_FILTER_V6 00453 generic map ( 00454 CLK_COR_MIN_LAT => 28 00455 ) 00456 port map ( 00457 USER_RXCHARISK => RxDataK_v6pcie4((2 * i) + 1 downto 2 * i), --O 00458 USER_RXDATA => RxData_v6pcie3((16 * i) + 15 downto (16 * i) + 0), --O 00459 USER_RXVALID => RxValid_v6pcie8(i), --O 00460 USER_RXELECIDLE => RxElecIdle_v6pcie5(i), --O 00461 USER_RX_STATUS => RxStatus_v6pcie7((3 * i) + 2 downto (3 * i)), --O 00462 USER_RX_PHY_STATUS => PhyStatus_v6pcie1(i), --O 00463 GT_RXCHARISK => GTX_RxDataK((2 * i) + 1 downto 2 * i), --I 00464 GT_RXDATA => GTX_RxData((16 * i) + 15 downto (16 * i) + 0), --I 00465 GT_RXVALID => GTX_RxValid(i), --I 00466 GT_RXELECIDLE => GTX_RxElecIdle(i), --I 00467 GT_RX_STATUS => GTX_RxStatus((3 * i) + 2 downto (3 * i)), --I 00468 GT_RX_PHY_STATUS => PHYSTATUS_int(i), --I 00469 PLM_IN_L0 => plm_in_l0, --I 00470 PLM_IN_RS => plm_in_rs, --I 00471 USER_CLK => PCLK, --I 00472 RESET => v6pcie12 --I 00473 ); 00474 00475 v6pcie14(i) <= (TXRESETDONE_q(i) and GTX_RxResetDone_q(i)); --I 00476 00477 GTX_TX_SYNC : GTX_TX_SYNC_RATE_V6 00478 generic map ( 00479 C_SIMULATION => to_integer(PL_FAST_TRAIN) 00480 ) 00481 port map ( 00482 ENPMAPHASEALIGN => TXENPMAPHASEALIGN(i), --O 00483 PMASETPHASE => TXPMASETPHASE(i), --O 00484 SYNC_DONE => SYNC_DONE(i), --O 00485 OUT_DIV_RESET => OUT_DIV_RESET(i), --O 00486 PCS_RESET => PCS_RESET(i), --O 00487 USER_PHYSTATUS => PHYSTATUS_int(i), --O 00488 TXALIGNDISABLE => TXDLYALIGNDISABLE(i), --O 00489 DELAYALIGNRESET => TXDLYALIGNRESET(i), --O 00490 USER_CLK => PCLK, --I 00491 RESET => v6pcie12, --I 00492 RATE => Rate, --I 00493 RATEDONE => TXRATEDONE(i), --I 00494 GT_PHYSTATUS => GTX_PhyStatus(i), --I 00495 RESETDONE => v6pcie14(i) --I 00496 ); 00497 00498 v6pcie15 <= not(GTReset_n); 00499 v6pcie16(i) <= ("10000000000" & OUT_DIV_RESET(i) & '0'); 00500 v6pcie18 <= ('0' & REFCLK); 00501 GTX_RxDataK((2 * i) + 1 downto 2 * i) <= v6pcie21((4*i)+1 downto (4*i)); 00502 GTX_RxData((16 * i) + 15 downto (16 * i) + 0) <= v6pcie23((32*i)+15 downto (32*i)); 00503 v6pcie24 <= ('1' & Rate); 00504 v6pcie25(i) <= not(GTReset_n) or local_pcs_reset or PCS_RESET(i); 00505 v6pcie26 <= (others => '1'); 00506 v6pcie27((4 * i) + 3 downto (4 * i) + 0) <= ("000" & GTX_TxCompliance(i)); 00507 v6pcie28((4 * i) + 3 downto (4 * i) + 0) <= (TxDataK_dummy(1 downto 0) & GTX_TxDataK((2 * i) + 1 downto 2 * i)); 00508 v6pcie29((32 * i) + 31 downto (32 * i) + 0) <= (TxData_dummy(15 downto 0) & GTX_TxData((16 * i) + 15 downto (16 * i) + 0)); 00509 00510 v6pcie30 <= (TxMargin & "00"); 00511 00512 GTX : GTXE1 00513 generic map ( 00514 TX_DRIVE_MODE => "PIPE", 00515 TX_DEEMPH_1 => "10010", 00516 TX_MARGIN_FULL_0 => "1001101", 00517 TX_CLK_SOURCE => "RXPLL", 00518 POWER_SAVE => "0000110100", 00519 CM_TRIM => "01", 00520 PMA_CDR_SCAN => x"640404C", 00521 PMA_CFG => x"0040000040000000003", 00522 RCV_TERM_GND => TRUE, 00523 RCV_TERM_VTTRX => FALSE, 00524 RX_DLYALIGN_EDGESET => "00010", 00525 RX_DLYALIGN_LPFINC => "0110", 00526 RX_DLYALIGN_OVRDSETTING => "10000000", 00527 TERMINATION_CTRL => "00000", 00528 TERMINATION_OVRD => FALSE, 00529 TX_DLYALIGN_LPFINC => "0110", 00530 TX_DLYALIGN_OVRDSETTING => "10000000", 00531 TXPLL_CP_CFG => pll_cp_cfg_sel(REF_CLK_FREQ), 00532 OOBDETECT_THRESHOLD => "011", 00533 RXPLL_CP_CFG => pll_cp_cfg_sel(REF_CLK_FREQ), 00534 ------------------------------------------------------------------------- 00535 -- TX_DETECT_RX_CFG => x"1832", 00536 ------------------------------------------------------------------------- 00537 TX_TDCC_CFG => "11", 00538 BIAS_CFG => x"00000", 00539 AC_CAP_DIS => FALSE, 00540 DFE_CFG => "00011011", 00541 SIM_TX_ELEC_IDLE_LEVEL => "1", 00542 SIM_RECEIVER_DETECT_PASS => TRUE, 00543 RX_EN_REALIGN_RESET_BUF => FALSE, 00544 TX_IDLE_ASSERT_DELAY => "100", -- TX-idle-set-to-idle (13 UI) 00545 TX_IDLE_DEASSERT_DELAY => "010", -- TX-idle-to-diff (7 UI) 00546 CHAN_BOND_SEQ_2_CFG => "11111", -- 5'b11111 for PCIE mode, 5'b00000 for other modes 00547 CHAN_BOND_KEEP_ALIGN => TRUE, 00548 RX_IDLE_HI_CNT => "1000", 00549 RX_IDLE_LO_CNT => "0000", 00550 RX_EN_IDLE_RESET_BUF => TRUE, 00551 TX_DATA_WIDTH => 20, 00552 RX_DATA_WIDTH => 20, 00553 ALIGN_COMMA_WORD => 1, 00554 CHAN_BOND_1_MAX_SKEW => 7, 00555 CHAN_BOND_2_MAX_SKEW => 1, 00556 CHAN_BOND_SEQ_1_1 => "0001000101", -- D5.2 (end TS2) 00557 CHAN_BOND_SEQ_1_2 => "0001000101", -- D5.2 (end TS2) 00558 CHAN_BOND_SEQ_1_3 => "0001000101", -- D5.2 (end TS2) 00559 CHAN_BOND_SEQ_1_4 => "0110111100", -- K28.5 (COM) 00560 CHAN_BOND_SEQ_1_ENABLE => "1111", -- order is 4321 00561 CHAN_BOND_SEQ_2_1 => "0100111100", -- K28.1 (FTS) 00562 CHAN_BOND_SEQ_2_2 => "0100111100", -- K28.1 (FTS) 00563 CHAN_BOND_SEQ_2_3 => "0110111100", -- K28.5 (COM) 00564 CHAN_BOND_SEQ_2_4 => "0100111100", -- K28.1 (FTS) 00565 CHAN_BOND_SEQ_2_ENABLE => "1111", -- order is 4321 00566 CHAN_BOND_SEQ_2_USE => TRUE, 00567 CHAN_BOND_SEQ_LEN => 4, -- 1..4 00568 RX_CLK25_DIVIDER => clk_div(REF_CLK_FREQ), 00569 TX_CLK25_DIVIDER => clk_div(REF_CLK_FREQ), 00570 CLK_COR_ADJ_LEN => 1, -- 1..4 00571 CLK_COR_DET_LEN => 1, -- 1..4 00572 CLK_COR_INSERT_IDLE_FLAG => FALSE, 00573 CLK_COR_KEEP_IDLE => FALSE, 00574 CLK_COR_MAX_LAT => 30, 00575 CLK_COR_MIN_LAT => 28, 00576 CLK_COR_PRECEDENCE => TRUE, 00577 CLK_CORRECT_USE => TRUE, 00578 CLK_COR_REPEAT_WAIT => 0, 00579 CLK_COR_SEQ_1_1 => "0100011100", -- K28.0 (SKP) 00580 CLK_COR_SEQ_1_2 => "0000000000", 00581 CLK_COR_SEQ_1_3 => "0000000000", 00582 CLK_COR_SEQ_1_4 => "0000000000", 00583 CLK_COR_SEQ_1_ENABLE => "1111", 00584 CLK_COR_SEQ_2_1 => "0000000000", 00585 CLK_COR_SEQ_2_2 => "0000000000", 00586 CLK_COR_SEQ_2_3 => "0000000000", 00587 CLK_COR_SEQ_2_4 => "0000000000", 00588 CLK_COR_SEQ_2_ENABLE => "1111", 00589 CLK_COR_SEQ_2_USE => FALSE, 00590 COMMA_10B_ENABLE => "1111111111", 00591 COMMA_DOUBLE => FALSE, 00592 DEC_MCOMMA_DETECT => TRUE, 00593 DEC_PCOMMA_DETECT => TRUE, 00594 DEC_VALID_COMMA_ONLY => TRUE, 00595 MCOMMA_10B_VALUE => "1010000011", 00596 MCOMMA_DETECT => TRUE, 00597 PCI_EXPRESS_MODE => TRUE, 00598 PCOMMA_10B_VALUE => "0101111100", 00599 PCOMMA_DETECT => TRUE, 00600 RXPLL_DIVSEL_FB => pll_div(REF_CLK_FREQ), -- 1..5, 8, 10 00601 TXPLL_DIVSEL_FB => pll_div(REF_CLK_FREQ), -- 1..5, 8, 10 00602 RXPLL_DIVSEL_REF => 1, -- 1..6, 8, 10, 12, 16, 20 00603 TXPLL_DIVSEL_REF => 1, -- 1..6, 8, 10, 12, 16, 20 00604 RXPLL_DIVSEL_OUT => 2, -- 1, 2, 4 00605 TXPLL_DIVSEL_OUT => 2, -- 1, 2, 4 00606 RXPLL_DIVSEL45_FB => 5, 00607 TXPLL_DIVSEL45_FB => 5, 00608 RX_BUFFER_USE => TRUE, 00609 RX_DECODE_SEQ_MATCH => TRUE, 00610 RX_LOS_INVALID_INCR => 8, -- power of 2: 1..128 00611 RX_LOSS_OF_SYNC_FSM => FALSE, 00612 RX_LOS_THRESHOLD => 128, -- power of 2: 4..512 00613 RX_SLIDE_MODE => "OFF", -- 00=OFF 01=AUTO 10=PCS 11=PMA 00614 RX_XCLK_SEL => "RXREC", 00615 TX_BUFFER_USE => FALSE, -- Must be set to FALSE for use by PCIE 00616 TX_XCLK_SEL => "TXUSR", -- Must be set to TXUSR for use by PCIE 00617 TXPLL_LKDET_CFG => "101", 00618 RX_EYE_SCANMODE => "00", 00619 RX_EYE_OFFSET => x"4C", 00620 PMA_RX_CFG => x"05ce008", 00621 TRANS_TIME_NON_P2 => x"02", -- Reduced simulation time 00622 TRANS_TIME_FROM_P2 => x"03c", -- Reduced simulation time 00623 TRANS_TIME_TO_P2 => x"064", -- Reduced simulation time 00624 TRANS_TIME_RATE => x"D7", -- Reduced simulation time 00625 SHOW_REALIGN_COMMA => FALSE, 00626 TX_PMADATA_OPT => '1', -- Lockup latch between PCS and PMA 00627 PMA_TX_CFG => x"80082", -- Aligns posedge of USRCLK 00628 TXOUTCLK_CTRL => "TXPLLREFCLK_DIV1" 00629 ) 00630 port map ( 00631 COMFINISH => open, 00632 COMINITDET => open, 00633 COMSASDET => open, 00634 COMWAKEDET => open, 00635 DADDR => daddr((8 * i) + 7 downto (8 * i)), 00636 DCLK => DRPCLK, 00637 DEN => den(i), 00638 DFECLKDLYADJ => "000000", -- Hex 13 00639 DFECLKDLYADJMON => open, 00640 DFEDLYOVRD => '1', 00641 DFEEYEDACMON => open, 00642 DFESENSCAL => open, 00643 DFETAP1 => "00000", 00644 DFETAP1MONITOR => open, 00645 DFETAP2 => tied_to_ground_vec_i(4 downto 0), 00646 DFETAP2MONITOR => open, 00647 DFETAP3 => tied_to_ground_vec_i(3 downto 0), 00648 DFETAP3MONITOR => open, 00649 DFETAP4 => tied_to_ground_vec_i(3 downto 0), 00650 DFETAP4MONITOR => open, 00651 DFETAPOVRD => '1', 00652 DI => din((16 * i) + 15 downto (16 * i)), 00653 DRDY => drdy(i), 00654 DRPDO => dout((16 * i) + 15 downto (16 * i)), 00655 DWE => dwe(i), 00656 GATERXELECIDLE => '0', 00657 GREFCLKRX => tied_to_ground_i, 00658 GREFCLKTX => tied_to_ground_i, 00659 GTXRXRESET => v6pcie15, 00660 GTXTEST => v6pcie16(i), 00661 GTXTXRESET => v6pcie15, 00662 LOOPBACK => "000", 00663 MGTREFCLKFAB => open, 00664 MGTREFCLKRX => v6pcie18, 00665 MGTREFCLKTX => v6pcie18, 00666 NORTHREFCLKRX => tied_to_ground_vec_i(1 downto 0), 00667 NORTHREFCLKTX => tied_to_ground_vec_i(1 downto 0), 00668 PHYSTATUS => GTX_PhyStatus(i), 00669 PLLRXRESET => '0', 00670 PLLTXRESET => '0', 00671 PRBSCNTRESET => '0', 00672 RXBUFRESET => '0', 00673 RXBUFSTATUS => open, 00674 RXBYTEISALIGNED => open, 00675 RXBYTEREALIGN => open, 00676 RXCDRRESET => '0', 00677 RXCHANBONDSEQ => open, 00678 RXCHANISALIGNED => ChanIsAligned_v6pcie0(i), 00679 RXCHANREALIGN => open, 00680 RXCHARISCOMMA => open, 00681 RXCHARISK => v6pcie21((4 * i) + 3 downto (4 * i)), 00682 RXCHBONDI => RXCHBOND(i), 00683 RXCHBONDLEVEL => GTX_RxChbondLevel((3 * i) + 2 downto (3 * i)), 00684 RXCHBONDMASTER => to_stdlogic(i = 0), 00685 RXCHBONDO => RXCHBOND(i + 1), 00686 RXCHBONDSLAVE => to_stdlogic(i > 0), 00687 RXCLKCORCNT => open, 00688 RXCOMMADET => open, 00689 RXCOMMADETUSE => '1', 00690 RXDATA => v6pcie23(((32 * i) + 31) downto (32 * i)), 00691 RXDATAVALID => open, 00692 RXDEC8B10BUSE => RXDEC8B10BUSE, 00693 RXDISPERR => open, 00694 RXDLYALIGNDISABLE => '1', 00695 RXELECIDLE => GTX_RxElecIdle(i), 00696 RXENCHANSYNC => '1', 00697 RXENMCOMMAALIGN => '1', 00698 RXENPCOMMAALIGN => '1', 00699 RXENPMAPHASEALIGN => '0', 00700 RXENPRBSTST => "000", 00701 RXENSAMPLEALIGN => '0', 00702 RXDLYALIGNMONENB => '1', 00703 RXEQMIX => "0110000011", 00704 RXGEARBOXSLIP => '0', 00705 RXHEADER => open, 00706 RXHEADERVALID => open, 00707 RXLOSSOFSYNC => open, 00708 RXN => GTX_RXN(i), 00709 RXNOTINTABLE => open, 00710 RXOVERSAMPLEERR => open, 00711 RXP => GTX_RXP(i), 00712 RXPLLLKDET => RxPLLLkDet_v6pcie6(i), 00713 RXPLLLKDETEN => '1', 00714 RXPLLPOWERDOWN => '0', 00715 RXPLLREFSELDY => "000", 00716 RXPMASETPHASE => '0', 00717 RXPOLARITY => GTX_RxPolarity(i), 00718 RXPOWERDOWN => PowerDown((2 * i) + 1 downto (2 * i)), 00719 RXPRBSERR => open, 00720 RXRATE => v6pcie24, 00721 RXRATEDONE => open, 00722 RXRECCLK => RXRECCLK, 00723 RXRECCLKPCS => open, 00724 RXRESET => v6pcie25(i), 00725 RXRESETDONE => GTX_RxResetDone(i), 00726 RXRUNDISP => open, 00727 RXSLIDE => '0', 00728 RXSTARTOFSEQ => open, 00729 RXSTATUS => GTX_RxStatus((3 * i) + 2 downto (3 * i)), 00730 RXUSRCLK => PCLK, 00731 RXUSRCLK2 => PCLK, 00732 RXVALID => GTX_RxValid(i), 00733 SOUTHREFCLKRX => tied_to_ground_vec_i(1 downto 0), 00734 SOUTHREFCLKTX => tied_to_ground_vec_i(1 downto 0), 00735 TSTCLK0 => '0', 00736 TSTCLK1 => '0', 00737 TSTIN => v6pcie26, 00738 TSTOUT => open, 00739 TXBUFDIFFCTRL => "111", 00740 TXBUFSTATUS => open, 00741 TXBYPASS8B10B => TXBYPASS8B10B(3 downto 0), 00742 TXCHARDISPMODE => v6pcie27((4 * i) + 3 downto (4 * i) + 0), 00743 TXCHARDISPVAL => "0000", 00744 TXCHARISK => v6pcie28((4 * i) + 3 downto (4 * i) + 0), 00745 TXCOMINIT => '0', 00746 TXCOMSAS => '0', 00747 TXCOMWAKE => '0', 00748 TXDATA => v6pcie29((32 * i) + 31 downto (32 * i) + 0), 00749 TXDEEMPH => TxDeemph, 00750 TXDETECTRX => TxDetectRx, 00751 TXDIFFCTRL => "1111", 00752 TXDLYALIGNDISABLE => TXDLYALIGNDISABLE(i), 00753 TXDLYALIGNRESET => TXDLYALIGNRESET(i), 00754 TXELECIDLE => GTX_TxElecIdle(i), 00755 TXENC8B10BUSE => '1', 00756 TXENPMAPHASEALIGN => TXENPMAPHASEALIGN(i), 00757 TXENPRBSTST => tied_to_ground_vec_i(2 downto 0), 00758 TXGEARBOXREADY => open, 00759 TXHEADER => tied_to_ground_vec_i(2 downto 0), 00760 TXINHIBIT => '0', 00761 TXKERR => open, 00762 TXMARGIN => v6pcie30, 00763 TXN => GTX_TXN(i), 00764 TXOUTCLK => TXOCLK(i), 00765 TXOUTCLKPCS => open, 00766 TXP => GTX_TXP(i), 00767 TXPDOWNASYNCH => TXPdownAsynch, 00768 TXPLLLKDET => open, 00769 TXPLLLKDETEN => '0', 00770 TXPLLPOWERDOWN => '0', 00771 TXPLLREFSELDY => "000", 00772 TXPMASETPHASE => TXPMASETPHASE(i), 00773 TXPOLARITY => '0', 00774 TXPOSTEMPHASIS => tied_to_ground_vec_i(4 downto 0), 00775 TXPOWERDOWN => PowerDown((2 * i) + 1 downto (2 * i)), 00776 TXPRBSFORCEERR => tied_to_ground_i, 00777 TXPREEMPHASIS => tied_to_ground_vec_i(3 downto 0), 00778 TXRATE => v6pcie24, 00779 TXRESET => v6pcie25(i), 00780 TXRESETDONE => TXRESETDONE(i), 00781 TXRUNDISP => open, 00782 TXSEQUENCE => tied_to_ground_vec_i(6 downto 0), 00783 TXSTARTSEQ => tied_to_ground_i, 00784 TXSWING => TxSwing, 00785 TXUSRCLK => PCLK, 00786 TXUSRCLK2 => PCLK, 00787 USRCODEERR => tied_to_ground_i, 00788 IGNORESIGDET => tied_to_ground_i, 00789 PERFCLKRX => tied_to_ground_i, 00790 PERFCLKTX => tied_to_ground_i, 00791 RXDLYALIGNMONITOR => open, 00792 RXDLYALIGNOVERRIDE => '0', 00793 RXDLYALIGNRESET => tied_to_ground_i, 00794 RXDLYALIGNSWPPRECURB => '1', 00795 RXDLYALIGNUPDSW => '0', 00796 TXDLYALIGNMONITOR => open, 00797 TXDLYALIGNOVERRIDE => '0', 00798 TXDLYALIGNUPDSW => '0', 00799 TXDLYALIGNMONENB => '1', 00800 TXRATEDONE => TXRATEDONE(i) 00801 ); 00802 00803 end generate; 00804 00805 00806 end v6_pcie; 00807
1.7.4