|
DS_DMA
|
00001 ------------------------------------------------------------------------------- 00002 -- 00003 -- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved. 00004 -- 00005 -- This file contains confidential and proprietary information 00006 -- of Xilinx, Inc. and is protected under U.S. and 00007 -- international copyright and other intellectual property 00008 -- laws. 00009 -- 00010 -- DISCLAIMER 00011 -- This disclaimer is not a license and does not grant any 00012 -- rights to the materials distributed herewith. Except as 00013 -- otherwise provided in a valid license issued to you by 00014 -- Xilinx, and to the maximum extent permitted by applicable 00015 -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 00016 -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 00017 -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 00018 -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 00019 -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 00020 -- (2) Xilinx shall not be liable (whether in contract or tort, 00021 -- including negligence, or under any other theory of 00022 -- liability) for any loss or damage of any kind or nature 00023 -- related to, arising under or in connection with these 00024 -- materials, including for any direct, or any indirect, 00025 -- special, incidental, or consequential loss or damage 00026 -- (including loss of data, profits, goodwill, or any type of 00027 -- loss or damage suffered as a result of any action brought 00028 -- by a third party) even if such damage or loss was 00029 -- reasonably foreseeable or Xilinx had been advised of the 00030 -- possibility of the same. 00031 -- 00032 -- CRITICAL APPLICATIONS 00033 -- Xilinx products are not designed or intended to be fail- 00034 -- safe, or for use in any application requiring fail-safe 00035 -- performance, such as life-support or safety devices or 00036 -- systems, Class III medical devices, nuclear facilities, 00037 -- applications related to the deployment of airbags, or any 00038 -- other applications that could lead to death, personal 00039 -- injury, or severe property or environmental damage 00040 -- (individually and collectively, "Critical 00041 -- Applications"). Customer assumes the sole risk and 00042 -- liability of any use of Xilinx products in Critical 00043 -- Applications, subject only to applicable laws and 00044 -- regulations governing limitations on product liability. 00045 -- 00046 -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 00047 -- PART OF THIS FILE AT ALL TIMES. 00048 -- 00049 ------------------------------------------------------------------------------- 00050 -- Project : Virtex-6 Integrated Block for PCI Express 00051 -- File : pcie_pipe_lane_v6.vhd 00052 -- Version : 2.3 00053 ---- Description: PIPE per lane module for Virtex6 PCIe Block 00054 ---- 00055 ---- 00056 ---- 00057 ---------------------------------------------------------------------------------- 00058 00059 library ieee; 00060 use ieee.std_logic_1164.all; 00061 00062 entity pcie_pipe_lane_v6 is 00063 generic ( 00064 PIPE_PIPELINE_STAGES : integer := 0 -- 0 - 0 stages, 1 - 1 stage, 2 - 2 stages 00065 ); 00066 port ( 00067 pipe_rx_char_is_k_o : out std_logic_vector(1 downto 0); 00068 pipe_rx_data_o : out std_logic_vector(15 downto 0); 00069 pipe_rx_valid_o : out std_logic; 00070 pipe_rx_chanisaligned_o : out std_logic; 00071 pipe_rx_status_o : out std_logic_vector(2 downto 0); 00072 pipe_rx_phy_status_o : out std_logic; 00073 pipe_rx_elec_idle_o : out std_logic; 00074 pipe_rx_polarity_i : in std_logic; 00075 pipe_tx_compliance_i : in std_logic; 00076 pipe_tx_char_is_k_i : in std_logic_vector(1 downto 0); 00077 pipe_tx_data_i : in std_logic_vector(15 downto 0); 00078 pipe_tx_elec_idle_i : in std_logic; 00079 pipe_tx_powerdown_i : in std_logic_vector(1 downto 0); 00080 pipe_rx_char_is_k_i : in std_logic_vector(1 downto 0); 00081 pipe_rx_data_i : in std_logic_vector(15 downto 0); 00082 pipe_rx_valid_i : in std_logic; 00083 pipe_rx_chanisaligned_i : in std_logic; 00084 pipe_rx_status_i : in std_logic_vector(2 downto 0); 00085 pipe_rx_phy_status_i : in std_logic; 00086 pipe_rx_elec_idle_i : in std_logic; 00087 pipe_rx_polarity_o : out std_logic; 00088 pipe_tx_compliance_o : out std_logic; 00089 pipe_tx_char_is_k_o : out std_logic_vector(1 downto 0); 00090 pipe_tx_data_o : out std_logic_vector(15 downto 0); 00091 pipe_tx_elec_idle_o : out std_logic; 00092 pipe_tx_powerdown_o : out std_logic_vector(1 downto 0); 00093 pipe_clk : in std_logic; 00094 rst_n : in std_logic 00095 ); 00096 end pcie_pipe_lane_v6; 00097 00098 architecture v6_pcie of pcie_pipe_lane_v6 is 00099 00100 --******************************************************************// 00101 -- Reality check. // 00102 --******************************************************************// 00103 00104 constant TCQ : integer := 1; -- clock to out delay model 00105 signal pipe_rx_char_is_k_q : std_logic_vector(1 downto 0); 00106 signal pipe_rx_data_q : std_logic_vector(15 downto 0); 00107 signal pipe_rx_valid_q : std_logic; 00108 signal pipe_rx_chanisaligned_q : std_logic; 00109 signal pipe_rx_status_q : std_logic_vector(2 downto 0); 00110 signal pipe_rx_phy_status_q : std_logic; 00111 signal pipe_rx_elec_idle_q : std_logic; 00112 00113 signal pipe_rx_polarity_q : std_logic; 00114 signal pipe_tx_compliance_q : std_logic; 00115 signal pipe_tx_char_is_k_q : std_logic_vector(1 downto 0); 00116 signal pipe_tx_data_q : std_logic_vector(15 downto 0); 00117 signal pipe_tx_elec_idle_q : std_logic; 00118 signal pipe_tx_powerdown_q : std_logic_vector(1 downto 0); 00119 00120 signal pipe_rx_char_is_k_qq : std_logic_vector(1 downto 0); 00121 signal pipe_rx_data_qq : std_logic_vector(15 downto 0); 00122 signal pipe_rx_valid_qq : std_logic; 00123 signal pipe_rx_chanisaligned_qq : std_logic; 00124 signal pipe_rx_status_qq : std_logic_vector(2 downto 0); 00125 signal pipe_rx_phy_status_qq : std_logic; 00126 signal pipe_rx_elec_idle_qq : std_logic; 00127 00128 signal pipe_rx_polarity_qq : std_logic; 00129 signal pipe_tx_compliance_qq : std_logic; 00130 signal pipe_tx_char_is_k_qq : std_logic_vector(1 downto 0); 00131 signal pipe_tx_data_qq : std_logic_vector(15 downto 0); 00132 signal pipe_tx_elec_idle_qq : std_logic; 00133 signal pipe_tx_powerdown_qq : std_logic_vector(1 downto 0); 00134 begin 00135 00136 v6pcie0 : if (PIPE_PIPELINE_STAGES = 0) generate 00137 00138 pipe_rx_char_is_k_o <= pipe_rx_char_is_k_i; 00139 pipe_rx_data_o <= pipe_rx_data_i; 00140 pipe_rx_valid_o <= pipe_rx_valid_i; 00141 pipe_rx_chanisaligned_o <= pipe_rx_chanisaligned_i; 00142 pipe_rx_status_o <= pipe_rx_status_i; 00143 pipe_rx_phy_status_o <= pipe_rx_phy_status_i; 00144 pipe_rx_elec_idle_o <= pipe_rx_elec_idle_i; 00145 00146 pipe_rx_polarity_o <= pipe_rx_polarity_i; 00147 pipe_tx_compliance_o <= pipe_tx_compliance_i; 00148 pipe_tx_char_is_k_o <= pipe_tx_char_is_k_i; 00149 pipe_tx_data_o <= pipe_tx_data_i; 00150 pipe_tx_elec_idle_o <= pipe_tx_elec_idle_i; 00151 pipe_tx_powerdown_o <= pipe_tx_powerdown_i; 00152 00153 end generate; 00154 v6pcie1 : if (PIPE_PIPELINE_STAGES = 1) generate 00155 00156 process (pipe_clk) 00157 begin 00158 if (pipe_clk'event and pipe_clk = '1') then 00159 00160 if (rst_n = '1') then 00161 00162 pipe_rx_char_is_k_q <= "00" after (TCQ)*1 ps; 00163 pipe_rx_data_q <= "0000000000000000" after (TCQ)*1 ps; 00164 pipe_rx_valid_q <= '0' after (TCQ)*1 ps; 00165 pipe_rx_chanisaligned_q <= '0' after (TCQ)*1 ps; 00166 pipe_rx_status_q <= "000" after (TCQ)*1 ps; 00167 pipe_rx_phy_status_q <= '0' after (TCQ)*1 ps; 00168 00169 pipe_rx_elec_idle_q <= '0' after (TCQ)*1 ps; 00170 pipe_rx_polarity_q <= '0' after (TCQ)*1 ps; 00171 pipe_tx_compliance_q <= '0' after (TCQ)*1 ps; 00172 pipe_tx_char_is_k_q <= "00" after (TCQ)*1 ps; 00173 pipe_tx_data_q <= "0000000000000000" after (TCQ)*1 ps; 00174 pipe_tx_elec_idle_q <= '1' after (TCQ)*1 ps; 00175 00176 pipe_tx_powerdown_q <= "10" after (TCQ)*1 ps; 00177 else 00178 00179 pipe_rx_char_is_k_q <= pipe_rx_char_is_k_i after (TCQ)*1 ps; 00180 pipe_rx_data_q <= pipe_rx_data_i after (TCQ)*1 ps; 00181 pipe_rx_valid_q <= pipe_rx_valid_i after (TCQ)*1 ps; 00182 pipe_rx_chanisaligned_q <= pipe_rx_chanisaligned_i after (TCQ)*1 ps; 00183 pipe_rx_status_q <= pipe_rx_status_i after (TCQ)*1 ps; 00184 pipe_rx_phy_status_q <= pipe_rx_phy_status_i after (TCQ)*1 ps; 00185 00186 pipe_rx_elec_idle_q <= pipe_rx_elec_idle_i after (TCQ)*1 ps; 00187 pipe_rx_polarity_q <= pipe_rx_polarity_i after (TCQ)*1 ps; 00188 pipe_tx_compliance_q <= pipe_tx_compliance_i after (TCQ)*1 ps; 00189 pipe_tx_char_is_k_q <= pipe_tx_char_is_k_i after (TCQ)*1 ps; 00190 pipe_tx_data_q <= pipe_tx_data_i after (TCQ)*1 ps; 00191 pipe_tx_elec_idle_q <= pipe_tx_elec_idle_i after (TCQ)*1 ps; 00192 00193 pipe_tx_powerdown_q <= pipe_tx_powerdown_i after (TCQ)*1 ps; 00194 end if; 00195 end if; 00196 end process; 00197 00198 00199 pipe_rx_char_is_k_o <= pipe_rx_char_is_k_q; 00200 pipe_rx_data_o <= pipe_rx_data_q; 00201 pipe_rx_valid_o <= pipe_rx_valid_q; 00202 pipe_rx_chanisaligned_o <= pipe_rx_chanisaligned_q; 00203 pipe_rx_status_o <= pipe_rx_status_q; 00204 pipe_rx_phy_status_o <= pipe_rx_phy_status_q; 00205 pipe_rx_elec_idle_o <= pipe_rx_elec_idle_q; 00206 00207 pipe_rx_polarity_o <= pipe_rx_polarity_q; 00208 pipe_tx_compliance_o <= pipe_tx_compliance_q; 00209 pipe_tx_char_is_k_o <= pipe_tx_char_is_k_q; 00210 pipe_tx_data_o <= pipe_tx_data_q; 00211 pipe_tx_elec_idle_o <= pipe_tx_elec_idle_q; 00212 pipe_tx_powerdown_o <= pipe_tx_powerdown_q; 00213 00214 end generate; 00215 v6pcie3 : if (PIPE_PIPELINE_STAGES = 2) generate 00216 00217 process (pipe_clk) 00218 begin 00219 if (pipe_clk'event and pipe_clk = '1') then 00220 00221 if (rst_n = '1') then 00222 00223 pipe_rx_char_is_k_q <= "00" after (TCQ)*1 ps; 00224 pipe_rx_data_q <= "0000000000000000" after (TCQ)*1 ps; 00225 pipe_rx_valid_q <= '0' after (TCQ)*1 ps; 00226 pipe_rx_chanisaligned_q <= '0' after (TCQ)*1 ps; 00227 pipe_rx_status_q <= "000" after (TCQ)*1 ps; 00228 pipe_rx_phy_status_q <= '0' after (TCQ)*1 ps; 00229 00230 pipe_rx_elec_idle_q <= '0' after (TCQ)*1 ps; 00231 pipe_rx_polarity_q <= '0' after (TCQ)*1 ps; 00232 pipe_tx_compliance_q <= '0' after (TCQ)*1 ps; 00233 pipe_tx_char_is_k_q <= "00" after (TCQ)*1 ps; 00234 pipe_tx_data_q <= "0000000000000000" after (TCQ)*1 ps; 00235 pipe_tx_elec_idle_q <= '1' after (TCQ)*1 ps; 00236 pipe_tx_powerdown_q <= "10" after (TCQ)*1 ps; 00237 00238 pipe_rx_char_is_k_qq <= "00" after (TCQ)*1 ps; 00239 pipe_rx_data_qq <= "0000000000000000" after (TCQ)*1 ps; 00240 pipe_rx_valid_qq <= '0' after (TCQ)*1 ps; 00241 pipe_rx_chanisaligned_qq <= '0' after (TCQ)*1 ps; 00242 pipe_rx_status_qq <= "000" after (TCQ)*1 ps; 00243 pipe_rx_phy_status_qq <= '0' after (TCQ)*1 ps; 00244 00245 pipe_rx_elec_idle_qq <= '0' after (TCQ)*1 ps; 00246 pipe_rx_polarity_qq <= '0' after (TCQ)*1 ps; 00247 pipe_tx_compliance_qq <= '0' after (TCQ)*1 ps; 00248 pipe_tx_char_is_k_qq <= "00" after (TCQ)*1 ps; 00249 pipe_tx_data_qq <= "0000000000000000" after (TCQ)*1 ps; 00250 pipe_tx_elec_idle_qq <= '1' after (TCQ)*1 ps; 00251 pipe_tx_powerdown_qq <= "10" after (TCQ)*1 ps; 00252 else 00253 00254 pipe_rx_char_is_k_q <= pipe_rx_char_is_k_i after (TCQ)*1 ps; 00255 pipe_rx_data_q <= pipe_rx_data_i after (TCQ)*1 ps; 00256 pipe_rx_valid_q <= pipe_rx_valid_i after (TCQ)*1 ps; 00257 pipe_rx_chanisaligned_q <= pipe_rx_chanisaligned_i after (TCQ)*1 ps; 00258 pipe_rx_status_q <= pipe_rx_status_i after (TCQ)*1 ps; 00259 pipe_rx_phy_status_q <= pipe_rx_phy_status_i after (TCQ)*1 ps; 00260 00261 pipe_rx_elec_idle_q <= pipe_rx_elec_idle_i after (TCQ)*1 ps; 00262 pipe_rx_polarity_q <= pipe_rx_polarity_i after (TCQ)*1 ps; 00263 pipe_tx_compliance_q <= pipe_tx_compliance_i after (TCQ)*1 ps; 00264 pipe_tx_char_is_k_q <= pipe_tx_char_is_k_i after (TCQ)*1 ps; 00265 pipe_tx_data_q <= pipe_tx_data_i after (TCQ)*1 ps; 00266 pipe_tx_elec_idle_q <= pipe_tx_elec_idle_i after (TCQ)*1 ps; 00267 pipe_tx_powerdown_q <= pipe_tx_powerdown_i after (TCQ)*1 ps; 00268 00269 pipe_rx_char_is_k_qq <= pipe_rx_char_is_k_q after (TCQ)*1 ps; 00270 pipe_rx_data_qq <= pipe_rx_data_q after (TCQ)*1 ps; 00271 pipe_rx_valid_qq <= pipe_rx_valid_q after (TCQ)*1 ps; 00272 pipe_rx_chanisaligned_qq <= pipe_rx_chanisaligned_q after (TCQ)*1 ps; 00273 pipe_rx_status_qq <= pipe_rx_status_q after (TCQ)*1 ps; 00274 pipe_rx_phy_status_qq <= pipe_rx_phy_status_q after (TCQ)*1 ps; 00275 00276 pipe_rx_elec_idle_qq <= pipe_rx_elec_idle_q after (TCQ)*1 ps; 00277 pipe_rx_polarity_qq <= pipe_rx_polarity_q after (TCQ)*1 ps; 00278 pipe_tx_compliance_qq <= pipe_tx_compliance_q after (TCQ)*1 ps; 00279 pipe_tx_char_is_k_qq <= pipe_tx_char_is_k_q after (TCQ)*1 ps; 00280 pipe_tx_data_qq <= pipe_tx_data_q after (TCQ)*1 ps; 00281 pipe_tx_elec_idle_qq <= pipe_tx_elec_idle_q after (TCQ)*1 ps; 00282 pipe_tx_powerdown_qq <= pipe_tx_powerdown_q after (TCQ)*1 ps; 00283 end if; 00284 end if; 00285 end process; 00286 00287 pipe_rx_char_is_k_o <= pipe_rx_char_is_k_qq; 00288 pipe_rx_data_o <= pipe_rx_data_qq; 00289 pipe_rx_valid_o <= pipe_rx_valid_qq; 00290 pipe_rx_chanisaligned_o <= pipe_rx_chanisaligned_qq; 00291 pipe_rx_status_o <= pipe_rx_status_qq; 00292 pipe_rx_phy_status_o <= pipe_rx_phy_status_qq; 00293 pipe_rx_elec_idle_o <= pipe_rx_elec_idle_qq; 00294 00295 pipe_rx_polarity_o <= pipe_rx_polarity_qq; 00296 pipe_tx_compliance_o <= pipe_tx_compliance_qq; 00297 pipe_tx_char_is_k_o <= pipe_tx_char_is_k_qq; 00298 pipe_tx_data_o <= pipe_tx_data_qq; 00299 pipe_tx_elec_idle_o <= pipe_tx_elec_idle_qq; 00300 pipe_tx_powerdown_o <= pipe_tx_powerdown_qq; 00301 00302 end generate; 00303 00304 end v6_pcie; 00305 00306
1.7.4