DS_DMA
Constants | Signals | Processes
v6_pcie Architecture Reference
Граф наследования:v6_pcie:
pcie_pipe_lane_v6 v6_pcie pcie_pipe_v6 v6_pcie pcie_2_0_v6 v6_pcie v6_pcie cl_v6pcie_m1 cl_v6pcie_x4 pcie_core64_m4 pcie_core64_m4 pcie_core64_m4_pkg pcie_core64_m5 pcie_core64_m5 pcie_core64_m5_pkg

Полный список членов класса



Processes

PROCESS_70  ( pipe_clk )
PROCESS_71  ( pipe_clk )

Constants

TCQ  integer := 1

Signals

pipe_rx_char_is_k_q  std_logic_vector ( 1 downto 0 )
pipe_rx_data_q  std_logic_vector ( 15 downto 0 )
pipe_rx_valid_q  std_logic
pipe_rx_chanisaligned_q  std_logic
pipe_rx_status_q  std_logic_vector ( 2 downto 0 )
pipe_rx_phy_status_q  std_logic
pipe_rx_elec_idle_q  std_logic
pipe_rx_polarity_q  std_logic
pipe_tx_compliance_q  std_logic
pipe_tx_char_is_k_q  std_logic_vector ( 1 downto 0 )
pipe_tx_data_q  std_logic_vector ( 15 downto 0 )
pipe_tx_elec_idle_q  std_logic
pipe_tx_powerdown_q  std_logic_vector ( 1 downto 0 )
pipe_rx_char_is_k_qq  std_logic_vector ( 1 downto 0 )
pipe_rx_data_qq  std_logic_vector ( 15 downto 0 )
pipe_rx_valid_qq  std_logic
pipe_rx_chanisaligned_qq  std_logic
pipe_rx_status_qq  std_logic_vector ( 2 downto 0 )
pipe_rx_phy_status_qq  std_logic
pipe_rx_elec_idle_qq  std_logic
pipe_rx_polarity_qq  std_logic
pipe_tx_compliance_qq  std_logic
pipe_tx_char_is_k_qq  std_logic_vector ( 1 downto 0 )
pipe_tx_data_qq  std_logic_vector ( 15 downto 0 )
pipe_tx_elec_idle_qq  std_logic
pipe_tx_powerdown_qq  std_logic_vector ( 1 downto 0 )

Подробное описание

См. определение в файле pcie_pipe_lane_v6.vhd строка 98


Объявления и описания членов класса находятся в файле: