Граф наследования:pcie_pipe_lane_v6:
Architectures | |
| v6_pcie | Architecture |
Libraries | |
| ieee | |
Packages | |
| std_logic_1164 | |
Generics | |
| PIPE_PIPELINE_STAGES | integer := 0 |
Ports | |
| pipe_rx_char_is_k_o | out std_logic_vector ( 1 downto 0 ) |
| pipe_rx_data_o | out std_logic_vector ( 15 downto 0 ) |
| pipe_rx_valid_o | out std_logic |
| pipe_rx_chanisaligned_o | out std_logic |
| pipe_rx_status_o | out std_logic_vector ( 2 downto 0 ) |
| pipe_rx_phy_status_o | out std_logic |
| pipe_rx_elec_idle_o | out std_logic |
| pipe_rx_polarity_i | in std_logic |
| pipe_tx_compliance_i | in std_logic |
| pipe_tx_char_is_k_i | in std_logic_vector ( 1 downto 0 ) |
| pipe_tx_data_i | in std_logic_vector ( 15 downto 0 ) |
| pipe_tx_elec_idle_i | in std_logic |
| pipe_tx_powerdown_i | in std_logic_vector ( 1 downto 0 ) |
| pipe_rx_char_is_k_i | in std_logic_vector ( 1 downto 0 ) |
| pipe_rx_data_i | in std_logic_vector ( 15 downto 0 ) |
| pipe_rx_valid_i | in std_logic |
| pipe_rx_chanisaligned_i | in std_logic |
| pipe_rx_status_i | in std_logic_vector ( 2 downto 0 ) |
| pipe_rx_phy_status_i | in std_logic |
| pipe_rx_elec_idle_i | in std_logic |
| pipe_rx_polarity_o | out std_logic |
| pipe_tx_compliance_o | out std_logic |
| pipe_tx_char_is_k_o | out std_logic_vector ( 1 downto 0 ) |
| pipe_tx_data_o | out std_logic_vector ( 15 downto 0 ) |
| pipe_tx_elec_idle_o | out std_logic |
| pipe_tx_powerdown_o | out std_logic_vector ( 1 downto 0 ) |
| pipe_clk | in std_logic |
| rst_n | in std_logic |
Подробное описание
См. определение в файле pcie_pipe_lane_v6.vhd строка 62
Объявления и описания членов класса находятся в файле:
- pcie_src/pcie_core64_m1/source_virtex6/pcie_pipe_lane_v6.vhd
