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DS_DMA
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00001 ------------------------------------------------------------------------------- 00002 -- 00003 -- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved. 00004 -- 00005 -- This file contains confidential and proprietary information 00006 -- of Xilinx, Inc. and is protected under U.S. and 00007 -- international copyright and other intellectual property 00008 -- laws. 00009 -- 00010 -- DISCLAIMER 00011 -- This disclaimer is not a license and does not grant any 00012 -- rights to the materials distributed herewith. Except as 00013 -- otherwise provided in a valid license issued to you by 00014 -- Xilinx, and to the maximum extent permitted by applicable 00015 -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 00016 -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 00017 -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 00018 -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 00019 -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 00020 -- (2) Xilinx shall not be liable (whether in contract or tort, 00021 -- including negligence, or under any other theory of 00022 -- liability) for any loss or damage of any kind or nature 00023 -- related to, arising under or in connection with these 00024 -- materials, including for any direct, or any indirect, 00025 -- special, incidental, or consequential loss or damage 00026 -- (including loss of data, profits, goodwill, or any type of 00027 -- loss or damage suffered as a result of any action brought 00028 -- by a third party) even if such damage or loss was 00029 -- reasonably foreseeable or Xilinx had been advised of the 00030 -- possibility of the same. 00031 -- 00032 -- CRITICAL APPLICATIONS 00033 -- Xilinx products are not designed or intended to be fail- 00034 -- safe, or for use in any application requiring fail-safe 00035 -- performance, such as life-support or safety devices or 00036 -- systems, Class III medical devices, nuclear facilities, 00037 -- applications related to the deployment of airbags, or any 00038 -- other applications that could lead to death, personal 00039 -- injury, or severe property or environmental damage 00040 -- (individually and collectively, "Critical 00041 -- Applications"). Customer assumes the sole risk and 00042 -- liability of any use of Xilinx products in Critical 00043 -- Applications, subject only to applicable laws and 00044 -- regulations governing limitations on product liability. 00045 -- 00046 -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 00047 -- PART OF THIS FILE AT ALL TIMES. 00048 -- 00049 ------------------------------------------------------------------------------- 00050 -- Project : Virtex-6 Integrated Block for PCI Express 00051 -- File : pcie_pipe_misc_v6.vhd 00052 -- Version : 2.3 00053 ---- Description: Misc PIPE module for Virtex6 PCIe Block 00054 ---- 00055 ---- 00056 ---- 00057 ---------------------------------------------------------------------------------- 00058 00059 library ieee; 00060 use ieee.std_logic_1164.all; 00061 00062 entity pcie_pipe_misc_v6 is 00063 generic ( 00064 PIPE_PIPELINE_STAGES : integer := 0 -- 0 - 0 stages, 1 - 1 stage, 2 - 2 stages 00065 00066 ); 00067 port ( 00068 pipe_tx_rcvr_det_i : in std_logic; 00069 pipe_tx_reset_i : in std_logic; 00070 pipe_tx_rate_i : in std_logic; 00071 pipe_tx_deemph_i : in std_logic; 00072 pipe_tx_margin_i : in std_logic_vector(2 downto 0); 00073 pipe_tx_swing_i : in std_logic; 00074 pipe_tx_rcvr_det_o : out std_logic; 00075 pipe_tx_reset_o : out std_logic; 00076 pipe_tx_rate_o : out std_logic; 00077 pipe_tx_deemph_o : out std_logic; 00078 pipe_tx_margin_o : out std_logic_vector(2 downto 0); 00079 pipe_tx_swing_o : out std_logic; 00080 pipe_clk : in std_logic; 00081 rst_n : in std_logic 00082 ); 00083 end pcie_pipe_misc_v6; 00084 00085 architecture v6_pcie of pcie_pipe_misc_v6 is 00086 00087 --******************************************************************// 00088 -- Reality check. // 00089 --******************************************************************// 00090 00091 constant TCQ : integer := 1; -- clock to out delay model 00092 00093 signal pipe_tx_rcvr_det_q : std_logic; 00094 signal pipe_tx_reset_q : std_logic; 00095 signal pipe_tx_rate_q : std_logic; 00096 signal pipe_tx_deemph_q : std_logic; 00097 signal pipe_tx_margin_q : std_logic_vector(2 downto 0); 00098 signal pipe_tx_swing_q : std_logic; 00099 00100 signal pipe_tx_rcvr_det_qq : std_logic; 00101 signal pipe_tx_reset_qq : std_logic; 00102 signal pipe_tx_rate_qq : std_logic; 00103 signal pipe_tx_deemph_qq : std_logic; 00104 signal pipe_tx_margin_qq : std_logic_vector(2 downto 0); 00105 signal pipe_tx_swing_qq : std_logic; 00106 begin 00107 00108 v6pcie0 : if (PIPE_PIPELINE_STAGES = 0) generate 00109 00110 pipe_tx_rcvr_det_o <= pipe_tx_rcvr_det_i; 00111 pipe_tx_reset_o <= pipe_tx_reset_i; 00112 pipe_tx_rate_o <= pipe_tx_rate_i; 00113 pipe_tx_deemph_o <= pipe_tx_deemph_i; 00114 pipe_tx_margin_o <= pipe_tx_margin_i; 00115 pipe_tx_swing_o <= pipe_tx_swing_i; 00116 00117 end generate; 00118 v6pcie1 : if (PIPE_PIPELINE_STAGES = 1) generate 00119 00120 process (pipe_clk) 00121 begin 00122 if (pipe_clk'event and pipe_clk = '1') then 00123 00124 if (rst_n = '1') then 00125 00126 pipe_tx_rcvr_det_q <= '0' after (TCQ)*1 ps; 00127 pipe_tx_reset_q <= '1' after (TCQ)*1 ps; 00128 pipe_tx_rate_q <= '0' after (TCQ)*1 ps; 00129 pipe_tx_deemph_q <= '1' after (TCQ)*1 ps; 00130 pipe_tx_margin_q <= "000" after (TCQ)*1 ps; 00131 pipe_tx_swing_q <= '0' after (TCQ)*1 ps; 00132 else 00133 00134 pipe_tx_rcvr_det_q <= pipe_tx_rcvr_det_i after (TCQ)*1 ps; 00135 pipe_tx_reset_q <= pipe_tx_reset_i after (TCQ)*1 ps; 00136 pipe_tx_rate_q <= pipe_tx_rate_i after (TCQ)*1 ps; 00137 pipe_tx_deemph_q <= pipe_tx_deemph_i after (TCQ)*1 ps; 00138 pipe_tx_margin_q <= pipe_tx_margin_i after (TCQ)*1 ps; 00139 pipe_tx_swing_q <= pipe_tx_swing_i after (TCQ)*1 ps; 00140 end if; 00141 end if; 00142 end process; 00143 00144 pipe_tx_rcvr_det_o <= pipe_tx_rcvr_det_q; 00145 pipe_tx_reset_o <= pipe_tx_reset_q; 00146 pipe_tx_rate_o <= pipe_tx_rate_q; 00147 pipe_tx_deemph_o <= pipe_tx_deemph_q; 00148 pipe_tx_margin_o <= pipe_tx_margin_q; 00149 pipe_tx_swing_o <= pipe_tx_swing_q; 00150 00151 end generate; 00152 v6pcie2 : if (PIPE_PIPELINE_STAGES = 2) generate 00153 00154 process (pipe_clk) 00155 begin 00156 if (pipe_clk'event and pipe_clk = '1') then 00157 00158 if (rst_n = '1') then 00159 00160 pipe_tx_rcvr_det_q <= '0' after (TCQ)*1 ps; 00161 pipe_tx_reset_q <= '1' after (TCQ)*1 ps; 00162 pipe_tx_rate_q <= '0' after (TCQ)*1 ps; 00163 pipe_tx_deemph_q <= '1' after (TCQ)*1 ps; 00164 pipe_tx_margin_q <= "000" after (TCQ)*1 ps; 00165 pipe_tx_swing_q <= '0' after (TCQ)*1 ps; 00166 00167 pipe_tx_rcvr_det_qq <= '0' after (TCQ)*1 ps; 00168 pipe_tx_reset_qq <= '1' after (TCQ)*1 ps; 00169 pipe_tx_rate_qq <= '0' after (TCQ)*1 ps; 00170 pipe_tx_deemph_qq <= '1' after (TCQ)*1 ps; 00171 pipe_tx_margin_qq <= "000" after (TCQ)*1 ps; 00172 pipe_tx_swing_qq <= '0' after (TCQ)*1 ps; 00173 else 00174 00175 pipe_tx_rcvr_det_q <= pipe_tx_rcvr_det_i after (TCQ)*1 ps; 00176 pipe_tx_reset_q <= pipe_tx_reset_i after (TCQ)*1 ps; 00177 pipe_tx_rate_q <= pipe_tx_rate_i after (TCQ)*1 ps; 00178 pipe_tx_deemph_q <= pipe_tx_deemph_i after (TCQ)*1 ps; 00179 pipe_tx_margin_q <= pipe_tx_margin_i after (TCQ)*1 ps; 00180 pipe_tx_swing_q <= pipe_tx_swing_i after (TCQ)*1 ps; 00181 00182 pipe_tx_rcvr_det_qq <= pipe_tx_rcvr_det_q after (TCQ)*1 ps; 00183 pipe_tx_reset_qq <= pipe_tx_reset_q after (TCQ)*1 ps; 00184 pipe_tx_rate_qq <= pipe_tx_rate_q after (TCQ)*1 ps; 00185 pipe_tx_deemph_qq <= pipe_tx_deemph_q after (TCQ)*1 ps; 00186 pipe_tx_margin_qq <= pipe_tx_margin_q after (TCQ)*1 ps; 00187 pipe_tx_swing_qq <= pipe_tx_swing_q after (TCQ)*1 ps; 00188 end if; 00189 end if; 00190 end process; 00191 00192 00193 pipe_tx_rcvr_det_o <= pipe_tx_rcvr_det_qq; 00194 pipe_tx_reset_o <= pipe_tx_reset_qq; 00195 pipe_tx_rate_o <= pipe_tx_rate_qq; 00196 pipe_tx_deemph_o <= pipe_tx_deemph_qq; 00197 pipe_tx_margin_o <= pipe_tx_margin_qq; 00198 pipe_tx_swing_o <= pipe_tx_swing_qq; 00199 00200 end generate; 00201 00202 end v6_pcie; 00203 00204
1.7.4