|
AMBPEX5_v20_SX50T_CORE
|
00001 --------------------------------------------------------------------------------------------------- 00002 -- 00003 -- Title : pb_adm_ctrl_m2 00004 -- Author : Dmitry Smekhov 00005 -- Company : Instrumental System 00006 -- E-mail : dsmv@insys.ru 00007 -- 00008 -- Version : 1.0 00009 -- 00010 --------------------------------------------------------------------------------------------------- 00011 -- 00012 -- Description : Узел декодирования адреса и подключения к тетрадам для шины PLD_BUS 00013 -- Поддерживается восемь тетрад 00014 -- 00015 -- Модификация 2. 00016 -- Увеличено число тактов на ответ. 00017 -- 00018 --------------------------------------------------------------------------------------------------- 00019 -- 00020 -- Version 1.0 01.04.2010 00021 -- Создан из pb_adm_ctrl v1.6 00022 -- 00023 --------------------------------------------------------------------------------------------------- 00024 00025 library IEEE; 00026 use IEEE.STD_LOGIC_1164.all; 00027 use ieee.std_logic_arith.all; 00028 00029 00030 library work; 00031 use work.adm2_pkg.all; 00032 00033 package pb_adm_ctrl_m2_pkg is 00034 00035 component pb_adm_ctrl_m2 is 00036 generic ( 00037 ---- Разрешение чтения из регистра DATA ---- 00038 trd1_in : in integer:=0; 00039 trd2_in : in integer:=0; 00040 trd3_in : in integer:=0; 00041 trd4_in : in integer:=0; 00042 trd5_in : in integer:=0; 00043 trd6_in : in integer:=0; 00044 trd7_in : in integer:=0; 00045 00046 ---- Разрешение чтения из регистра STATUS ---- 00047 trd1_st : in integer:=0; 00048 trd2_st : in integer:=0; 00049 trd3_st : in integer:=0; 00050 trd4_st : in integer:=0; 00051 trd5_st : in integer:=0; 00052 trd6_st : in integer:=0; 00053 trd7_st : in integer:=0; 00054 00055 00056 ---- Константы тетрады ---- 00057 rom0 : in bl_trd_rom; 00058 rom1 : in bl_trd_rom; 00059 rom2 : in bl_trd_rom; 00060 rom3 : in bl_trd_rom; 00061 rom4 : in bl_trd_rom; 00062 rom5 : in bl_trd_rom; 00063 rom6 : in bl_trd_rom; 00064 rom7 : in bl_trd_rom; 00065 00066 ---- Режим управления перепаковкой для тетрады 4 ---- 00067 ---- 0 - перепаковка 32->64 разрешается битом MAIN.MODE2[4] ---- 00068 ---- 2 - перепаковка разрешается при разрешении DRQ2 ---- 00069 trd4_mode : in integer:=0 00070 ); 00071 00072 port ( 00073 ---- GLOBAL ---- 00074 reset : in std_logic; -- 0 - сброс 00075 clk : in std_logic; -- тактовая частота 00076 00077 ---- PLD_BUS ---- 00078 lc_adr : in std_logic_vector( 6 downto 0 ); -- шина адреса 00079 lc_host_data : in std_logic_vector( 63 downto 0 ); -- шина данных, вход 00080 lc_data : out std_logic_vector( 63 downto 0 ); -- шина данных, выход 00081 lc_wr : in std_logic; -- 1 - запись 00082 lc_rd : in std_logic; -- 1 - чтение 00083 00084 00085 test_mode : in std_logic; -- 1 - тестовый режим 00086 00087 ---- Шина адреса для подключения к узлу начального тестирования тетрады MAIN ---- 00088 trd_host_adr : out std_logic_vector( 6 downto 0 ); 00089 00090 ---- Шина данных, через которую производиться запись в регистры тетрады ---- 00091 trd_host_data : out std_logic_vector( 63 downto 0 ); 00092 00093 ---- Шина данных, через которую производиться запись в регистр DATA тетрады 4 ---- 00094 trd4_host_data : out std_logic_vector( 63 downto 0 ); 00095 00096 ---- Комада управления для каждой тетрады ---- 00097 trd_host_cmd : out std_logic_array_16xbl_cmd; 00098 00099 ---- Выходы региста DATA от каждой тетрады ---- 00100 trd_data : in std_logic_array_16x64:=(others=>(others=>'0')); 00101 00102 ---- Выходы регистров STATUS, CMD_ADR, CMD_DATA от каждой тетрады ---- 00103 trd_cmd_data : in std_logic_array_16x16:=(others=>(others=>'0')); 00104 00105 ---- Сброс FIFO от каждой тетрады ---- 00106 trd_reset_fifo : in std_logic_array_16xbl_reset_fifo:=(others=>'0'); 00107 00108 ---- Запросы DMA от каждой тетрады ---- 00109 trd_drq : in std_logic_array_16xbl_drq:=(others=>(others=>'0')); 00110 00111 00112 ---- Источники прерываний и DRQ ---- 00113 int1 : in std_logic:='0'; 00114 00115 drq0 : in bl_drq:=('0', '0', '0'); 00116 drq1 : in bl_drq:=('0', '0', '0'); 00117 drq2 : in bl_drq:=('0', '0', '0'); 00118 drq3 : in bl_drq:=('0', '0', '0'); 00119 00120 ---- Выход DRQ и IRQ ---- 00121 irq1 : out std_logic; 00122 dmar0 : out std_logic; 00123 dmar1 : out std_logic; 00124 dmar2 : out std_logic; 00125 dmar3 : out std_logic 00126 00127 00128 ); 00129 end component; 00130 00131 end package pb_adm_ctrl_m2_pkg; 00132 00133 00134 library IEEE; 00135 use IEEE.STD_LOGIC_1164.all; 00136 use ieee.std_logic_arith.all; 00137 00138 00139 00140 -- synopsys translate_off 00141 library ieee; 00142 use ieee.vital_timing.all; 00143 00144 library unisim; 00145 use unisim.VCOMPONENTS.all; 00146 -- synopsys translate_on 00147 00148 library work; 00149 use work.adm2_pkg.all; 00150 00151 entity pb_adm_ctrl_m2 is 00152 generic ( 00153 ---- Разрешение чтения из регистра DATA ---- 00154 trd1_in : in integer:=0; 00155 trd2_in : in integer:=0; 00156 trd3_in : in integer:=0; 00157 trd4_in : in integer:=0; 00158 trd5_in : in integer:=0; 00159 trd6_in : in integer:=0; 00160 trd7_in : in integer:=0; 00161 00162 ---- Разрешение чтения из регистра STATUS ---- 00163 trd1_st : in integer:=0; 00164 trd2_st : in integer:=0; 00165 trd3_st : in integer:=0; 00166 trd4_st : in integer:=0; 00167 trd5_st : in integer:=0; 00168 trd6_st : in integer:=0; 00169 trd7_st : in integer:=0; 00170 00171 00172 ---- Константы тетрады ---- 00173 rom0 : in bl_trd_rom; 00174 rom1 : in bl_trd_rom; 00175 rom2 : in bl_trd_rom; 00176 rom3 : in bl_trd_rom; 00177 rom4 : in bl_trd_rom; 00178 rom5 : in bl_trd_rom; 00179 rom6 : in bl_trd_rom; 00180 rom7 : in bl_trd_rom; 00181 00182 ---- Режим управления перепаковкой для тетрады 4 ---- 00183 ---- 0 - перепаковка 32->64 разрешается битом MAIN.MODE2[4] ---- 00184 ---- 2 - перепаковка разрешается при разрешении DRQ2 ---- 00185 trd4_mode : in integer:=0 00186 00187 ); 00188 00189 port ( 00190 ---- GLOBAL ---- 00191 reset : in std_logic; -- 0 - сброс 00192 clk : in std_logic; -- тактовая частота 00193 00194 ---- PLD_BUS ---- 00195 lc_adr : in std_logic_vector( 6 downto 0 ); -- шина адреса 00196 lc_host_data : in std_logic_vector( 63 downto 0 ); -- шина данных, вход 00197 lc_data : out std_logic_vector( 63 downto 0 ); -- шина данных, выход 00198 lc_wr : in std_logic; -- 1 - запись 00199 lc_rd : in std_logic; -- 1 - чтение 00200 00201 00202 test_mode : in std_logic; -- 1 - тестовый режим 00203 00204 ---- Шина адреса для подключения к узлу начального тестирования тетрады MAIN ---- 00205 trd_host_adr : out std_logic_vector( 6 downto 0 ); 00206 00207 ---- Шина данных, через которую производиться запись в регистры тетрады ---- 00208 trd_host_data : out std_logic_vector( 63 downto 0 ); 00209 00210 ---- Шина данных, через которую производиться запись в регистр DATA тетрады 4 ---- 00211 trd4_host_data : out std_logic_vector( 63 downto 0 ); 00212 00213 ---- Комада управления для каждой тетрады ---- 00214 trd_host_cmd : out std_logic_array_16xbl_cmd; 00215 00216 ---- Выходы региста DATA от каждой тетрады ---- 00217 trd_data : in std_logic_array_16x64:=(others=>(others=>'0')); 00218 00219 ---- Выходы регистров STATUS, CMD_ADR, CMD_DATA от каждой тетрады ---- 00220 trd_cmd_data : in std_logic_array_16x16:=(others=>(others=>'0')); 00221 00222 ---- Сброс FIFO от каждой тетрады ---- 00223 trd_reset_fifo : in std_logic_array_16xbl_reset_fifo:=(others=>'0'); 00224 00225 ---- Запросы DMA от каждой тетрады ---- 00226 trd_drq : in std_logic_array_16xbl_drq:=(others=>(others=>'0')); 00227 00228 ---- Источники прерываний и DRQ ---- 00229 int1 : in std_logic:='0'; 00230 00231 drq0 : in bl_drq:=('0', '0', '0'); 00232 drq1 : in bl_drq:=('0', '0', '0'); 00233 drq2 : in bl_drq:=('0', '0', '0'); 00234 drq3 : in bl_drq:=('0', '0', '0'); 00235 00236 ---- Выход DRQ и IRQ ---- 00237 irq1 : out std_logic; 00238 dmar0 : out std_logic; 00239 dmar1 : out std_logic; 00240 dmar2 : out std_logic; 00241 dmar3 : out std_logic 00242 00243 00244 ); 00245 end pb_adm_ctrl_m2; 00246 00247 00248 00249 architecture pb_adm_ctrl_m2 of pb_adm_ctrl_m2 is 00250 00251 00252 00253 00254 component ctrl_dram256x16_v2 is 00255 port ( 00256 addra: in std_logic_vector(7 downto 0); 00257 addrb: in std_logic_vector(7 downto 0); 00258 clka: in std_logic; 00259 clkb: in std_logic; 00260 dina: in std_logic_vector(15 downto 0); 00261 doutb: out std_logic_vector(15 downto 0); 00262 sinita: in std_logic; 00263 ena: in std_logic; 00264 enb: in std_logic; 00265 wea: in std_logic); 00266 end component; 00267 00268 component RAMB16_S18 00269 -- synopsys translate_off 00270 generic ( 00271 00272 00273 00274 WRITE_MODE : string := "WRITE_FIRST"; 00275 INIT : bit_vector := X"00000"; 00276 SRVAL : bit_vector := X"00000"; 00277 00278 00279 INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00280 INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00281 INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00282 INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00283 INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00284 INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00285 INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00286 INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00287 INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00288 INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00289 INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00290 INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00291 INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00292 INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00293 INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00294 INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00295 INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00296 INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00297 INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00298 INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00299 INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00300 INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00301 INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00302 INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00303 INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00304 INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00305 INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00306 INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00307 INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00308 INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00309 INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00310 INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00311 INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00312 INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00313 INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00314 INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00315 INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00316 INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00317 INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00318 INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00319 INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00320 INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00321 INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00322 INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00323 INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00324 INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00325 INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00326 INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00327 INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00328 INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00329 INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00330 INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00331 INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00332 INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00333 INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00334 INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00335 INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00336 INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00337 INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00338 INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00339 INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00340 INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00341 INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00342 INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00343 INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00344 INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00345 INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00346 INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00347 INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00348 INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00349 INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; 00350 INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" 00351 ); 00352 -- synopsys translate_on 00353 port ( 00354 DO : out STD_LOGIC_VECTOR (15 downto 0); 00355 DOP : out STD_LOGIC_VECTOR (1 downto 0); 00356 ADDR : in STD_LOGIC_VECTOR (9 downto 0); 00357 CLK : in STD_ULOGIC; 00358 DI : in STD_LOGIC_VECTOR (15 downto 0); 00359 DIP : in STD_LOGIC_VECTOR (1 downto 0); 00360 EN : in STD_ULOGIC; 00361 SSR : in STD_ULOGIC; 00362 WE : in STD_ULOGIC 00363 ); 00364 end component; 00365 00366 component ctrl_adsp_v2_decode_data_cs is 00367 generic( 00368 trd : in integer; -- номер тетрады 00369 reg : in integer -- номер регистра 00370 -- 0 - STATUS 00371 -- 1 - DATA 00372 -- 2 - CMD_ADR 00373 -- 3 - CMD_DATA 00374 ); 00375 port ( 00376 reset : in std_logic; -- 0 - сброс 00377 clk : in std_logic; -- тактовая частота 00378 cmd_data_en : in std_logic; -- 1 - разрешение декодирования CMD_DATA 00379 adr : in std_logic_vector( 4 downto 0 ); -- шина адреса 00380 rd : in std_logic; -- 0 - чтение данных 00381 data_cs : out std_logic -- 0 - чтение данных 00382 ); 00383 end component; 00384 00385 component ctrl_adsp_v2_decode_data_in_cs is 00386 port ( 00387 reset : in std_logic; -- 0 - сброс 00388 clk : in std_logic; -- тактовая частота 00389 cmd_adr : in std_logic_vector( 9 downto 8 ); -- косвенный адрес 00390 adr : in std_logic_vector( 4 downto 0 ); -- шина адреса 00391 rd : in std_logic; -- 0 - чтение данных 00392 data_cs : out std_logic -- 0 - чтение данных 00393 ); 00394 end component; 00395 00396 00397 component ctrl_adsp_v2_decode_ram_cs is 00398 generic ( 00399 reg : in integer -- номер регистра 00400 -- 0 - RAM 00401 -- 1 - ROM 00402 ); 00403 port ( 00404 reset : in std_logic; -- 0 - сброс 00405 clk : in std_logic; -- тактовая частота 00406 cmd_adr : in std_logic_vector( 9 downto 8 ); -- косвенный адрес 00407 adr : in std_logic_vector( 4 downto 0 ); -- шина адреса 00408 rd : in std_logic; -- 0 - чтение данных 00409 data_cs : out std_logic -- 0 - чтение данных 00410 ); 00411 end component; 00412 00413 component ctrl_adsp_v2_decode_data_we is 00414 generic( 00415 trd : in integer; -- номер тетрады 00416 reg : in integer -- номер регистра 00417 -- 0 - STATUS 00418 -- 1 - DATA 00419 -- 2 - CMD_ADR 00420 -- 3 - CMD_DATA 00421 ); 00422 port ( 00423 reset : in std_logic; -- 0 - сброс 00424 clk : in std_logic; -- тактовая частота 00425 adr : in std_logic_vector( 4 downto 0 ); -- шина адреса 00426 wr : in std_logic; -- 0 - запись данных 00427 data_we : out std_logic -- 1 - запись данных 00428 ); 00429 end component; 00430 00431 00432 component ctrl_adsp_v2_decode_cmd_adr_cs is 00433 port ( 00434 reset : in std_logic; -- 0 - сброс 00435 clk : in std_logic; -- тактовая частота 00436 adr : in std_logic_vector( 4 downto 0 ); -- шина адреса 00437 rd : in std_logic; -- 0 - чтение данных 00438 data_cs : out std_logic -- 0 - чтение данных 00439 ); 00440 end component; 00441 00442 00443 00444 component ctrl_mux8x48 is 00445 port ( 00446 ma: in std_logic_vector(47 downto 0); 00447 mb: in std_logic_vector(47 downto 0); 00448 mc: in std_logic_vector(47 downto 0); 00449 md: in std_logic_vector(47 downto 0); 00450 me: in std_logic_vector(47 downto 0); 00451 mf: in std_logic_vector(47 downto 0); 00452 mg: in std_logic_vector(47 downto 0); 00453 mh: in std_logic_vector(47 downto 0); 00454 s: in std_logic_vector(2 downto 0); 00455 o: out std_logic_vector(47 downto 0)); 00456 end component; 00457 00458 00459 component ctrl_mux16x16 is 00460 port ( 00461 ma: in std_logic_vector(15 downto 0); 00462 mb: in std_logic_vector(15 downto 0); 00463 mc: in std_logic_vector(15 downto 0); 00464 md: in std_logic_vector(15 downto 0); 00465 me: in std_logic_vector(15 downto 0); 00466 mf: in std_logic_vector(15 downto 0); 00467 mg: in std_logic_vector(15 downto 0); 00468 mh: in std_logic_vector(15 downto 0); 00469 maa: in std_logic_vector(15 downto 0); 00470 mab: in std_logic_vector(15 downto 0); 00471 mac: in std_logic_vector(15 downto 0); 00472 mad: in std_logic_vector(15 downto 0); 00473 mae: in std_logic_vector(15 downto 0); 00474 maf: in std_logic_vector(15 downto 0); 00475 mag: in std_logic_vector(15 downto 0); 00476 mah: in std_logic_vector(15 downto 0); 00477 s: in std_logic_vector(3 downto 0); 00478 o: out std_logic_vector(15 downto 0)); 00479 end component; 00480 00481 component ctrl_mux8x16r is 00482 port ( 00483 ma: in std_logic_vector(15 downto 0); 00484 mb: in std_logic_vector(15 downto 0); 00485 mc: in std_logic_vector(15 downto 0); 00486 md: in std_logic_vector(15 downto 0); 00487 me: in std_logic_vector(15 downto 0); 00488 mf: in std_logic_vector(15 downto 0); 00489 mg: in std_logic_vector(15 downto 0); 00490 mh: in std_logic_vector(15 downto 0); 00491 s: in std_logic_vector(2 downto 0); 00492 q: out std_logic_vector(15 downto 0); 00493 clk: in std_logic); 00494 end component; 00495 00496 00497 --component s_delay is 00498 -- port( 00499 -- i : in std_logic; -- входной сигнал 00500 -- o : out std_logic -- выходной сигнад 00501 -- ); 00502 --end component; 00503 00504 -- XST black box declaration 00505 --attribute box_type : string; 00506 --attribute BOX_TYPE of RAMB16_S18 : component is "BLACK_BOX"; 00507 00508 00509 00510 signal ms1 : std_logic; 00511 signal wrl1, wrl2, rd1, rd2: std_logic; 00512 signal adr1, adr2 : std_logic_vector( 6 downto 0 ); 00513 signal data2 : std_logic_vector( 63 downto 0 ); 00514 signal rd2z : std_logic; 00515 00516 signal data_out2 : std_logic_vector( 63 downto 0 ); 00517 00518 00519 00520 signal cmd_data2 : std_logic_vector( 15 downto 0 ); 00521 signal rom_data2 : std_logic_vector( 15 downto 0 ); 00522 signal sinit, dpram_en : std_logic; 00523 signal dpram_en0 : std_logic; 00524 signal addra : std_logic_vector( 9 downto 0 ); 00525 signal addra2 : std_logic_vector( 15 downto 0 ); 00526 signal dpram_cs2 : std_logic; 00527 00528 signal bl_status_cs : std_logic_vector( 7 downto 0 ); 00529 signal bl_data_cs : std_logic_vector( 7 downto 0 ); 00530 signal bl_cmd_data_cs : std_logic_vector( 7 downto 0 ); 00531 00532 signal bl_data_we : std_logic_vector( 7 downto 0 ); 00533 signal bl_cmd_adr_we : std_logic_vector( 7 downto 0 ); 00534 signal bl_cmd_adr_we1 : std_logic_vector( 7 downto 0 ); 00535 signal bl_cmd_data_we : std_logic_vector( 7 downto 0 ); 00536 signal bl_cmd_data_we1 : std_logic_vector( 7 downto 0 ); 00537 00538 signal ram_cs1, ram_cs2 : std_logic; 00539 signal rom_cs2 : std_logic; 00540 signal data_in_cs2 : std_logic; 00541 signal data_in_cs2_0 : std_logic; 00542 signal cmd_adr_cs2 : std_logic; 00543 00544 signal cmd0_adr, cmd1_adr, cmd2_adr, cmd3_adr: std_logic_vector( 15 downto 0 ); 00545 signal cmd4_adr, cmd5_adr, cmd6_adr, cmd7_adr: std_logic_vector( 15 downto 0 ); 00546 00547 signal rom_di : std_logic_vector( 15 downto 0 ); 00548 00549 signal sel_cmd_data : std_logic; -- 1 - чтение непосредственных регистров 00550 signal sel_cmd_ram : std_logic; -- 1 - чтение командных регистров 00551 signal sel_cmd_rom : std_logic; -- 1 - чтение констант 00552 00553 signal flyby1 : std_logic; -- 1 - выполнение цикла DMA 00554 signal ram_rom_cs : std_logic; 00555 signal en_ram : std_logic; 00556 00557 00558 signal ma, mb, mc, md, me, mf, mg, mh : std_logic_vector( 63 downto 0 ); 00559 signal maa, mab, mac, mad, mae, maf, mag, mah : std_logic_vector( 15 downto 0 ); 00560 00561 signal na, nb, nc, nd, ne, nf, ng, nh : std_logic_vector( 15 downto 0 ); 00562 00563 signal mux_sel : std_logic_vector( 3 downto 0 ); 00564 00565 signal flyby2 : std_logic; 00566 signal flag_data_we : std_logic_vector( 7 downto 0 ); 00567 signal main_mode2_4 : std_logic:='0'; 00568 signal trd4i_host_data : std_logic_vector( 63 downto 0 ); 00569 00570 signal flag_rd_block : std_logic_vector( 15 downto 0 ); 00571 signal flag_rd_repack : std_logic_vector( 15 downto 0 ); 00572 signal trd_repack_data : std_logic_array_16x64:=(others=>(others=>'0')); 00573 00574 signal lc_data_i : std_logic_vector( 63 downto 0 ); 00575 00576 function conv_rom( rom: in bl_trd_rom; mode: integer ) return bit_vector is 00577 variable ret: bit_vector( 255 downto 0 ); 00578 begin 00579 for i in 0 to 15 loop 00580 ret( i*16+15 downto i*16 ):=to_bitvector( rom( i+mode*16 ), '0' ); 00581 end loop; 00582 return ret; 00583 end conv_rom; 00584 00585 function conv_string( rom: in bl_trd_rom; mode: integer ) return string is 00586 variable str: string( 64 downto 1 ); 00587 00588 variable d : std_logic_vector( 15 downto 0 ); 00589 variable c : std_logic_vector( 3 downto 0 ); 00590 variable k : integer; 00591 begin 00592 00593 00594 00595 for i in 0 to 15 loop 00596 d:=rom( i+mode*16 ); 00597 for j in 0 to 3 loop 00598 c:=d( j*4+3 downto j*4 ); 00599 k:=i*4+j+1; 00600 case c is 00601 when x"0" => str(k) := '0'; 00602 when x"1" => str(k) := '1'; 00603 when x"2" => str(k) := '2'; 00604 when x"3" => str(k) := '3'; 00605 when x"4" => str(k) := '4'; 00606 when x"5" => str(k) := '5'; 00607 when x"6" => str(k) := '6'; 00608 when x"7" => str(k) := '7'; 00609 when x"8" => str(k) := '8'; 00610 when x"9" => str(k) := '9'; 00611 when x"A" => str(k) := 'A'; 00612 when x"B" => str(k) := 'B'; 00613 when x"C" => str(k) := 'C'; 00614 when x"D" => str(k) := 'D'; 00615 when x"E" => str(k) := 'E'; 00616 when x"F" => str(k) := 'F'; 00617 when others => null; 00618 end case; 00619 end loop; 00620 end loop; 00621 00622 return str; 00623 end conv_string; 00624 00625 00626 constant rom_init_00 : bit_vector( 255 downto 0 ):= conv_rom( rom0, 0 ); 00627 constant rom_init_01 : bit_vector( 255 downto 0 ):= conv_rom( rom0, 1 ); 00628 constant rom_init_02 : bit_vector( 255 downto 0 ):= conv_rom( rom1, 0 ); 00629 constant rom_init_03 : bit_vector( 255 downto 0 ):= conv_rom( rom1, 1 ); 00630 constant rom_init_04 : bit_vector( 255 downto 0 ):= conv_rom( rom2, 0 ); 00631 constant rom_init_05 : bit_vector( 255 downto 0 ):= conv_rom( rom2, 1 ); 00632 constant rom_init_06 : bit_vector( 255 downto 0 ):= conv_rom( rom3, 0 ); 00633 constant rom_init_07 : bit_vector( 255 downto 0 ):= conv_rom( rom3, 1 ); 00634 constant rom_init_08 : bit_vector( 255 downto 0 ):= conv_rom( rom4, 0 ); 00635 constant rom_init_09 : bit_vector( 255 downto 0 ):= conv_rom( rom4, 1 ); 00636 constant rom_init_0A : bit_vector( 255 downto 0 ):= conv_rom( rom5, 0 ); 00637 constant rom_init_0B : bit_vector( 255 downto 0 ):= conv_rom( rom5, 1 ); 00638 constant rom_init_0C : bit_vector( 255 downto 0 ):= conv_rom( rom6, 0 ); 00639 constant rom_init_0D : bit_vector( 255 downto 0 ):= conv_rom( rom6, 1 ); 00640 constant rom_init_0E : bit_vector( 255 downto 0 ):= conv_rom( rom7, 0 ); 00641 constant rom_init_0F : bit_vector( 255 downto 0 ):= conv_rom( rom7, 1 ); 00642 00643 00644 00645 constant str_init_00 : string:= conv_string( rom0, 0 ); 00646 constant str_init_01 : string:= conv_string( rom0, 1 ); 00647 constant str_init_02 : string:= conv_string( rom1, 0 ); 00648 constant str_init_03 : string:= conv_string( rom1, 1 ); 00649 constant str_init_04 : string:= conv_string( rom2, 0 ); 00650 constant str_init_05 : string:= conv_string( rom2, 1 ); 00651 constant str_init_06 : string:= conv_string( rom3, 0 ); 00652 constant str_init_07 : string:= conv_string( rom3, 1 ); 00653 constant str_init_08 : string:= conv_string( rom4, 0 ); 00654 constant str_init_09 : string:= conv_string( rom4, 1 ); 00655 constant str_init_0A : string:= conv_string( rom5, 0 ); 00656 constant str_init_0B : string:= conv_string( rom5, 1 ); 00657 constant str_init_0C : string:= conv_string( rom6, 0 ); 00658 constant str_init_0D : string:= conv_string( rom6, 1 ); 00659 constant str_init_0E : string:= conv_string( rom7, 0 ); 00660 constant str_init_0F : string:= conv_string( rom7, 1 ); 00661 00662 00663 attribute rom_style : string; 00664 attribute rom_style of rom : label is "block"; 00665 00666 attribute init_10 : string; 00667 attribute init_11 : string; 00668 attribute init_12 : string; 00669 attribute init_13 : string; 00670 attribute init_14 : string; 00671 attribute init_15 : string; 00672 attribute init_16 : string; 00673 attribute init_17 : string; 00674 attribute init_18 : string; 00675 attribute init_19 : string; 00676 attribute init_1A : string; 00677 attribute init_1B : string; 00678 attribute init_1C : string; 00679 attribute init_1D : string; 00680 attribute init_1E : string; 00681 attribute init_1F : string; 00682 00683 attribute init_10 of rom : label is str_init_00; 00684 attribute init_11 of rom : label is str_init_01; 00685 attribute init_12 of rom : label is str_init_02; 00686 attribute init_13 of rom : label is str_init_03; 00687 attribute init_14 of rom : label is str_init_04; 00688 attribute init_15 of rom : label is str_init_05; 00689 attribute init_16 of rom : label is str_init_06; 00690 attribute init_17 of rom : label is str_init_07; 00691 attribute init_18 of rom : label is str_init_08; 00692 attribute init_19 of rom : label is str_init_09; 00693 attribute init_1A of rom : label is str_init_0A; 00694 attribute init_1B of rom : label is str_init_0B; 00695 attribute init_1C of rom : label is str_init_0C; 00696 attribute init_1D of rom : label is str_init_0D; 00697 attribute init_1E of rom : label is str_init_0E; 00698 attribute init_1F of rom : label is str_init_0F; 00699 00700 begin 00701 00702 00703 rd1<= not lc_rd; 00704 00705 wrl1<= not lc_wr; 00706 00707 pr_ms2: process( reset, clk ) begin 00708 if( reset='0' ) then 00709 wrl2<='1'; rd2<='1'; 00710 elsif( rising_edge( clk ) ) then 00711 wrl2<=wrl1 after 1 ns; rd2<=rd1 after 1 ns; 00712 end if; 00713 end process; 00714 00715 00716 adr1<=lc_adr( 6 downto 0 ) when test_mode='0' else "0000010"; 00717 00718 pr_adr_in: process( clk ) begin 00719 if( rising_edge( clk ) ) then 00720 if( test_mode='1' ) then 00721 adr2<="0000010"; 00722 else 00723 adr2<=adr1; 00724 end if; 00725 end if; 00726 end process; 00727 00728 data2<=lc_host_data when rising_edge( clk ); 00729 trd_host_data<=data2; 00730 00731 pr_bl_adr_out: process( clk ) begin 00732 if( rising_edge( clk ) ) then 00733 trd_host_adr( 6 downto 0 )<=lc_adr( 6 downto 0 ); 00734 end if; 00735 end process; 00736 00737 rom: RAMB16_S18 00738 -- synopsys translate_off 00739 generic map ( 00740 INIT_10 => rom_init_00, 00741 INIT_11 => rom_init_01, 00742 INIT_12 => rom_init_02, 00743 INIT_13 => rom_init_03, 00744 INIT_14 => rom_init_04, 00745 INIT_15 => rom_init_05, 00746 INIT_16 => rom_init_06, 00747 INIT_17 => rom_init_07, 00748 INIT_18 => rom_init_08, 00749 INIT_19 => rom_init_09, 00750 INIT_1A => rom_init_0A, 00751 INIT_1B => rom_init_0B, 00752 INIT_1C => rom_init_0C, 00753 INIT_1D => rom_init_0D, 00754 INIT_1E => rom_init_0E, 00755 INIT_1F => rom_init_0F 00756 ) 00757 -- synopsys translate_on 00758 port map ( 00759 DO => rom_data2, 00760 ADDR(8 downto 0) => addra( 8 downto 0 ), 00761 ADDR(9) => '0' , 00762 CLK => clk, 00763 DI => data2( 15 downto 0 ), 00764 DIP => "00", 00765 EN => '1', 00766 SSR => '0', 00767 WE => dpram_en 00768 ); 00769 00770 en_ram <= ((dpram_en or ram_cs1) and not (addra(8)) )or (ram_cs1 and addra(8)); 00771 00772 addra2( 7 downto 5 )<=(others=>'0'); -- не используются 00773 addra2( 15 downto 10 )<=(others=>'0'); -- не используется 00774 00775 pr_addra: process( clk ) 00776 variable vsel: bit_vector( 2 downto 0 ); 00777 begin 00778 vsel:=to_bitvector( adr1( 5 downto 3 ), '0' ); 00779 if( rising_edge( clk ) ) then 00780 addra( 7 downto 5 )<=adr1( 5 downto 3 ); 00781 ram_cs1<=not rd1; 00782 case vsel is 00783 when "000" => 00784 addra( 4 downto 0 )<=cmd0_adr( 4 downto 0 ); 00785 addra( 9 downto 8 )<=cmd0_adr( 9 downto 8 ); 00786 when "001" => 00787 addra( 4 downto 0 )<=cmd1_adr( 4 downto 0 ); 00788 addra( 9 downto 8 )<=cmd1_adr( 9 downto 8); 00789 when "010" => 00790 addra( 4 downto 0 )<=cmd2_adr( 4 downto 0 ); 00791 addra( 9 downto 8 )<=cmd2_adr( 9 downto 8); 00792 when "011" => 00793 addra( 4 downto 0 )<=cmd3_adr( 4 downto 0 ); 00794 addra( 9 downto 8 )<=cmd3_adr( 9 downto 8); 00795 when "100" => 00796 addra( 4 downto 0 )<=cmd4_adr( 4 downto 0 ); 00797 addra( 9 downto 8 )<=cmd4_adr( 9 downto 8); 00798 when "101" => 00799 addra( 4 downto 0 )<=cmd5_adr( 4 downto 0 ); 00800 addra( 9 downto 8 )<=cmd5_adr( 9 downto 8); 00801 when "110" => 00802 addra( 4 downto 0 )<=cmd6_adr( 4 downto 0 ); 00803 addra( 9 downto 8 )<=cmd6_adr( 9 downto 8); 00804 when "111" => 00805 addra( 4 downto 0 )<=cmd7_adr( 4 downto 0 ); 00806 addra( 9 downto 8 )<=cmd7_adr( 9 downto 8); 00807 end case; 00808 addra2( 9 downto 8 )<=addra( 9 downto 8 ); 00809 addra2( 4 downto 0 )<=addra( 4 downto 0 ); 00810 end if; 00811 end process; 00812 00813 pr_dpram_en: process( clk ) 00814 variable ven: std_logic; 00815 begin 00816 ven:='0'; 00817 if( rising_edge( clk ) ) then 00818 if( test_mode='0' ) then 00819 if( wrl1='0' and adr1(2)='1' and adr1(1)='1' ) then ven:='1'; end if; 00820 end if; 00821 dpram_en0<=ven; 00822 end if; 00823 end process; 00824 00825 dpram_en <='1' when dpram_en0='1' and addra(9)='0' and addra(8)='0' else '0'; 00826 00827 00828 rd2z <= rd2 after 1 ns when rising_edge( clk ); 00829 gen_data_cs: for i in 0 to 7 generate 00830 00831 xstatus: ctrl_adsp_v2_decode_data_cs 00832 generic map( trd=>i, reg=>0 ) 00833 port map ( 00834 reset => reset, 00835 clk => clk, 00836 cmd_data_en =>'0', 00837 adr => adr1(5 downto 1), 00838 rd => rd1, 00839 data_cs => bl_status_cs(i) 00840 ); 00841 00842 xdata: ctrl_adsp_v2_decode_data_cs 00843 generic map( trd=>i, reg=>1 ) 00844 port map ( 00845 reset => reset, 00846 clk => clk, 00847 cmd_data_en =>'0', 00848 adr => adr2(5 downto 1), 00849 rd => rd2z, 00850 data_cs => bl_data_cs(i) 00851 ); 00852 00853 00854 xcmd_data: ctrl_adsp_v2_decode_data_cs 00855 generic map( trd=>i, reg=>3 ) 00856 port map( 00857 reset => reset, 00858 clk => clk, 00859 cmd_data_en =>sel_cmd_data , 00860 adr => adr1( 5 downto 1 ), 00861 rd => rd1, 00862 data_cs => bl_cmd_data_cs(i) 00863 ); 00864 00865 xdata_we: ctrl_adsp_v2_decode_data_we 00866 generic map( trd=>i, reg=>1 ) 00867 port map( 00868 reset => reset, 00869 clk => clk, 00870 adr => adr1( 5 downto 1 ), 00871 wr => wrl1, 00872 data_we => bl_data_we(i) 00873 ); 00874 00875 xcmd_adr_we: ctrl_adsp_v2_decode_data_we 00876 generic map( trd=>i, reg=>2 ) 00877 port map( 00878 reset => reset, 00879 clk => clk, 00880 adr => adr1( 5 downto 1 ), 00881 wr => wrl1, 00882 data_we => bl_cmd_adr_we(i) 00883 ); 00884 00885 xcmd_data_we: ctrl_adsp_v2_decode_data_we 00886 generic map( trd=>i, reg=>3 ) 00887 port map( 00888 reset => reset, 00889 clk => clk, 00890 adr => adr1( 5 downto 1 ), 00891 wr => wrl1, 00892 data_we => bl_cmd_data_we(i) 00893 ); 00894 00895 00896 end generate; 00897 00898 xcmd_ram: ctrl_adsp_v2_decode_ram_cs 00899 generic map( reg => 0 ) 00900 port map ( 00901 reset => reset, 00902 clk => clk, 00903 cmd_adr => addra( 9 downto 8 ), 00904 adr => adr2( 5 downto 1 ), 00905 rd => rd2, 00906 data_cs => ram_cs2 00907 ); 00908 00909 xcmd_rom: ctrl_adsp_v2_decode_ram_cs 00910 generic map( reg => 1 ) 00911 port map ( 00912 reset => reset, 00913 clk => clk, 00914 cmd_adr => addra( 9 downto 8 ), 00915 adr => adr2( 5 downto 1 ), 00916 rd => rd2, 00917 data_cs => rom_cs2 00918 ); 00919 00920 00921 xcmd_adr: ctrl_adsp_v2_decode_cmd_adr_cs 00922 port map( 00923 reset => reset, 00924 clk => clk, 00925 adr => adr2( 5 downto 1 ), 00926 rd => rd2, 00927 data_cs => cmd_adr_cs2 00928 ); 00929 00930 --sel_cmd_data <= addra(9); 00931 sel_cmd_ram <= '1' when addra(9)='0' and addra(8)='0' else '0'; 00932 sel_cmd_rom <= '1' when addra(9)='0' and addra(8)='1' else '0'; 00933 00934 pr_sel_cmd_data: process( adr1, cmd0_adr, cmd1_adr, cmd2_adr, cmd3_adr, 00935 cmd4_adr, cmd5_adr, cmd6_adr, cmd7_adr ) 00936 variable vsel: bit_vector( 2 downto 0 ); 00937 begin 00938 vsel:=to_bitvector( adr1( 5 downto 3 ), '0' ); 00939 case vsel is 00940 when "000" => sel_cmd_data <= cmd0_adr( 9 ); 00941 when "001" => sel_cmd_data <= cmd1_adr( 9 ); 00942 when "010" => sel_cmd_data <= cmd2_adr( 9 ); 00943 when "011" => sel_cmd_data <= cmd3_adr( 9 ); 00944 when "100" => sel_cmd_data <= cmd4_adr( 9 ); 00945 when "101" => sel_cmd_data <= cmd5_adr( 9 ); 00946 when "110" => sel_cmd_data <= cmd6_adr( 9 ); 00947 when "111" => sel_cmd_data <= cmd7_adr( 9 ); 00948 end case; 00949 end process; 00950 00951 00952 pr_cmd_adr: process( reset, clk ) begin 00953 if( reset='0' ) then 00954 cmd0_adr<=(others=>'0'); 00955 cmd1_adr<=(others=>'0'); 00956 cmd2_adr<=(others=>'0'); 00957 cmd3_adr<=(others=>'0'); 00958 cmd4_adr<=(others=>'0'); 00959 cmd5_adr<=(others=>'0'); 00960 cmd6_adr<=(others=>'0'); 00961 cmd7_adr<=(others=>'0'); 00962 elsif( rising_edge( clk ) ) then 00963 if( bl_cmd_adr_we(0)='1' ) then cmd0_adr( 9 downto 0 )<=data2( 9 downto 0 ); end if; 00964 if( bl_cmd_adr_we(1)='1' ) then cmd1_adr( 9 downto 0 )<=data2( 9 downto 0 ); end if; 00965 if( bl_cmd_adr_we(2)='1' ) then cmd2_adr( 9 downto 0 )<=data2( 9 downto 0 ); end if; 00966 if( bl_cmd_adr_we(3)='1' ) then cmd3_adr( 9 downto 0 )<=data2( 9 downto 0 ); end if; 00967 if( bl_cmd_adr_we(4)='1' ) then cmd4_adr( 9 downto 0 )<=data2( 9 downto 0 ); end if; 00968 if( bl_cmd_adr_we(5)='1' ) then cmd5_adr( 9 downto 0 )<=data2( 9 downto 0 ); end if; 00969 if( bl_cmd_adr_we(6)='1' ) then cmd6_adr( 9 downto 0 )<=data2( 9 downto 0 ); end if; 00970 if( bl_cmd_adr_we(7)='1' ) then cmd7_adr( 9 downto 0 )<=data2( 9 downto 0 ); end if; 00971 end if; 00972 end process; 00973 00974 pr_adr_we1: process( clk ) begin 00975 if( rising_edge( clk ) ) then 00976 bl_cmd_adr_we1<=bl_cmd_adr_we; 00977 end if; 00978 end process; 00979 00980 cmd0_adr( 15 downto 10 ) <= ( others=>'0' ); 00981 cmd1_adr( 15 downto 10 ) <= ( others=>'0' ); 00982 cmd2_adr( 15 downto 10 ) <= ( others=>'0' ); 00983 cmd3_adr( 15 downto 10 ) <= ( others=>'0' ); 00984 cmd4_adr( 15 downto 10 ) <= ( others=>'0' ); 00985 cmd5_adr( 15 downto 10 ) <= ( others=>'0' ); 00986 cmd6_adr( 15 downto 10 ) <= ( others=>'0' ); 00987 cmd7_adr( 15 downto 10 ) <= ( others=>'0' ); 00988 00989 ram_rom_cs <= ram_cs2 and rom_cs2; 00990 00991 00992 pr_irq: process( clk ) begin 00993 if( rising_edge( clk ) ) then 00994 irq1 <= int1; 00995 end if; 00996 end process; 00997 00998 00999 dmar0 <= '1' when drq0.en='1' and drq0.req='1' else '0'; 01000 dmar1 <= '1' when drq1.en='1' and drq1.req='1' else '0'; 01001 dmar2 <= '1' when drq2.en='1' and drq2.req='1' else '0'; 01002 dmar3 <= '1' when drq3.en='1' and drq3.req='1' else '0'; 01003 01004 -- 01005 --gen_cmd_data_we: for i in 0 to 7 generate 01006 -- 01007 --xcmd_data_we: s_delay port map( o=>bl_cmd_data_we1(i), i=>bl_cmd_data_we(i) ); 01008 -- 01009 --end generate; 01010 -- 01011 01012 bl_cmd_data_we1 <= bl_cmd_data_we; 01013 01014 gen_trd_cmd: for i in 0 to 7 generate 01015 01016 trd_host_cmd(i).data_we <=bl_data_we(i) and flag_data_we(i); 01017 trd_host_cmd(i).cmd_data_we <=bl_cmd_data_we1(i); 01018 trd_host_cmd(i).status_cs <=bl_status_cs(i); 01019 trd_host_cmd(i).data_cs <=bl_data_cs(i) or flag_rd_block(i); --flag_rd_repack(i); 01020 trd_host_cmd(i).data_oe <=bl_data_cs(i); 01021 trd_host_cmd(i).cmd_data_cs <=bl_cmd_data_cs(i); 01022 trd_host_cmd(i).cmd_adr_we <=bl_cmd_adr_we1(i); 01023 01024 end generate; 01025 01026 trd_host_cmd(0).adr <=cmd0_adr( 9 downto 0 ); 01027 trd_host_cmd(1).adr <=cmd1_adr( 9 downto 0 ); 01028 trd_host_cmd(2).adr <=cmd2_adr( 9 downto 0 ); 01029 trd_host_cmd(3).adr <=cmd3_adr( 9 downto 0 ); 01030 trd_host_cmd(4).adr <=cmd4_adr( 9 downto 0 ); 01031 trd_host_cmd(5).adr <=cmd5_adr( 9 downto 0 ); 01032 trd_host_cmd(6).adr <=cmd6_adr( 9 downto 0 ); 01033 trd_host_cmd(7).adr <=cmd7_adr( 9 downto 0 ); 01034 01035 01036 01037 01038 01039 01040 mux8: ctrl_mux8x48 01041 port map ( 01042 ma => ma( 63 downto 16 ), 01043 mb => mb( 63 downto 16 ), 01044 mc => mc( 63 downto 16 ), 01045 md => md( 63 downto 16 ), 01046 me => me( 63 downto 16 ), 01047 mf => mf( 63 downto 16 ), 01048 mg => mg( 63 downto 16 ), 01049 mh => mh( 63 downto 16 ), 01050 s => mux_sel( 2 downto 0 ), 01051 o => lc_data_i( 63 downto 16 ) ); 01052 01053 01054 01055 mux16: ctrl_mux16x16 01056 port map( 01057 ma => ma( 15 downto 0 ), 01058 mb => mb( 15 downto 0 ), 01059 mc => mc( 15 downto 0 ), 01060 md => md( 15 downto 0 ), 01061 me => me( 15 downto 0 ), 01062 mf => mf( 15 downto 0 ), 01063 mg => mg( 15 downto 0 ), 01064 mh => mh( 15 downto 0 ), 01065 maa => maa( 15 downto 0 ), 01066 mab => mab( 15 downto 0 ), 01067 mac => mac( 15 downto 0 ), 01068 mad => mad( 15 downto 0 ), 01069 mae => mae( 15 downto 0 ), 01070 maf => maf( 15 downto 0 ), 01071 mag => mag( 15 downto 0 ), 01072 mah => mah( 15 downto 0 ), 01073 s => mux_sel( 3 downto 0 ), 01074 o => lc_data_i( 15 downto 0 ) ); 01075 01076 lc_data <= lc_data_i after 1 ns when rising_edge( clk ); 01077 01078 ma <= trd_repack_data(0) after 1 ns when rising_edge( clk ); 01079 01080 xd1p: if( trd1_in=1 ) generate mb <= trd_repack_data(1) after 1 ns when rising_edge( clk ); end generate; 01081 xd1n: if( trd1_in=0 ) generate mb <= (others=>'0'); end generate; 01082 01083 xd2p: if( trd2_in=1 ) generate mc <= trd_repack_data(2) after 1 ns when rising_edge( clk ); end generate; 01084 xd2n: if( trd2_in=0 ) generate mc <= (others=>'0'); end generate; 01085 01086 xd3p: if( trd3_in=1 ) generate md <= trd_repack_data(3) after 1 ns when rising_edge( clk ); end generate; 01087 xd3n: if( trd3_in=0 ) generate md <= (others=>'0'); end generate; 01088 01089 xd4p: if( trd4_in=1 ) generate me <= trd_repack_data(4) after 1 ns when rising_edge( clk ); end generate; 01090 xd4n: if( trd4_in=0 ) generate me <= (others=>'0'); end generate; 01091 01092 xd5p: if( trd5_in=1 ) generate mf <= trd_repack_data(5) after 1 ns when rising_edge( clk ); end generate; 01093 xd5n: if( trd5_in=0 ) generate mf <= (others=>'0'); end generate; 01094 01095 xd6p: if( trd6_in=1 ) generate mg <= trd_repack_data(6) after 1 ns when rising_edge( clk ); end generate; 01096 xd6n: if( trd6_in=0 ) generate mg <= (others=>'0'); end generate; 01097 01098 xd7p: if( trd6_in=1 ) generate mh <= trd_repack_data(7) after 1 ns when rising_edge( clk ); end generate; 01099 xd7n: if( trd6_in=0 ) generate mh <= (others=>'0'); end generate; 01100 01101 01102 gen_repack: for ii in 0 to 7 generate 01103 01104 trd_repack_data(ii)( 31 downto 0 ) <= trd_data(ii)( 31 downto 0 ) when flag_rd_repack(ii)='0' else trd_data(ii)( 63 downto 32 ); 01105 trd_repack_data(ii)( 63 downto 32 ) <= trd_data(ii)( 63 downto 32 ); 01106 01107 pr_flag4: process( clk ) begin 01108 if( rising_edge( clk ) ) then 01109 if( trd_drq(ii).en='1' ) then 01110 flag_rd_repack(ii) <= '0' after 1 ns; 01111 flag_rd_block(ii) <= '0' after 1 ns; 01112 elsif( trd_reset_fifo(ii)='0' ) then 01113 flag_rd_repack(ii) <= '0' after 1 ns; 01114 flag_rd_block(ii) <= '1' after 1 ns; 01115 elsif( bl_data_cs(ii)='0' ) then 01116 flag_rd_repack(ii) <= not flag_rd_repack(ii) after 1 ns; 01117 flag_rd_block(ii) <= not flag_rd_block(ii) after 1 ns; 01118 end if; 01119 end if; 01120 end process; 01121 01122 end generate; 01123 01124 01125 01126 01127 maa <= rom_data2 after 1 ns when rising_edge( clk ); 01128 mab <= cmd_data2 after 1 ns when rising_edge( clk ); 01129 mac <= addra2 after 1 ns when rising_edge( clk ); 01130 01131 mad <= (others=>'-'); 01132 mae <= (others=>'-'); 01133 maf <= (others=>'-'); 01134 mag <= (others=>'-'); 01135 mah <= (others=>'-'); 01136 01137 01138 pr_mux_sel: process( clk ) begin 01139 if( rising_edge( clk ) ) then 01140 case( adr2( 2 downto 1 ) ) is 01141 when "00" => -- STATUS 01142 mux_sel <= "1001"; 01143 when "01" => -- DATA 01144 mux_sel( 2 downto 0 ) <= adr2( 5 downto 3 ); 01145 mux_sel( 3 ) <= '0'; 01146 when "10" => -- CMD_ADR 01147 mux_sel <= "1010"; 01148 when "11" => -- CMD_DATA 01149 mux_sel( 3 downto 1 ) <= "100"; 01150 mux_sel( 0 ) <= addra( 9 ); 01151 when others => null; 01152 end case; 01153 end if; 01154 end process; 01155 01156 01157 01158 mux_cmd: ctrl_mux8x16r 01159 port map ( 01160 ma => na, 01161 mb => nb, 01162 mc => nc, 01163 md => nd, 01164 me => ne, 01165 mf => nf, 01166 mg => ng, 01167 mh => nh, 01168 s => adr2( 5 downto 3 ), 01169 q => cmd_data2, 01170 clk => clk 01171 ); 01172 01173 na <= trd_cmd_data(0) after 1 ns when rising_edge( clk ); 01174 01175 xc1p: if( trd1_st=1 ) generate nb <= trd_cmd_data(1) after 1 ns when rising_edge( clk ); end generate; 01176 xc1n: if( trd1_st=0 ) generate nb <= (others=>'1'); end generate; 01177 01178 xc2p: if( trd2_st=1 ) generate nc <= trd_cmd_data(2) after 1 ns when rising_edge( clk ); end generate; 01179 xc2n: if( trd2_st=0 ) generate nc <= (others=>'1'); end generate; 01180 01181 xc3p: if( trd3_st=1 ) generate nd <= trd_cmd_data(3) after 1 ns when rising_edge( clk ); end generate; 01182 xc3n: if( trd3_st=0 ) generate nd <= (others=>'1'); end generate; 01183 01184 xc4p: if( trd4_st=1 ) generate ne <= trd_cmd_data(4) after 1 ns when rising_edge( clk ); end generate; 01185 xc4n: if( trd4_st=0 ) generate ne <= (others=>'1'); end generate; 01186 01187 xc5p: if( trd5_st=1 ) generate nf <= trd_cmd_data(5) after 1 ns when rising_edge( clk ); end generate; 01188 xc5n: if( trd5_st=0 ) generate nf <= (others=>'1'); end generate; 01189 01190 xc6p: if( trd6_st=1 ) generate ng <= trd_cmd_data(6) after 1 ns when rising_edge( clk ); end generate; 01191 xc6n: if( trd6_st=0 ) generate ng <= (others=>'1'); end generate; 01192 01193 xc7p: if( trd7_st=1 ) generate nh <= trd_cmd_data(7) after 1 ns when rising_edge( clk ); end generate; 01194 xc7n: if( trd7_st=0 ) generate nh <= (others=>'1'); end generate; 01195 01196 01197 01198 pr_flag_data_we4: process( clk ) begin 01199 if( rising_edge( clk ) ) then 01200 if( main_mode2_4='0' ) then 01201 flag_data_we(4) <= '1' after 1 ns; 01202 elsif( trd_reset_fifo( 4 )='0' ) then 01203 flag_data_we(4) <= '0' after 1 ns; 01204 elsif( bl_data_we( 4 )='1' ) then 01205 flag_data_we( 4 ) <= not flag_data_we( 4 ) after 1 ns; 01206 end if; 01207 end if; 01208 end process; 01209 01210 trd4i_host_data( 31 downto 0 ) <= data2( 31 downto 0 ) when rising_edge( clk ) and flag_data_we(4)='0' and bl_data_we(4)='1'; 01211 trd4i_host_data( 63 downto 32 ) <= data2( 31 downto 0 ); 01212 01213 trd4_host_data <= trd4i_host_data when main_mode2_4='1' else data2; 01214 01215 flag_data_we( 3 downto 0 ) <= (others=>'1'); 01216 flag_data_we( 7 downto 5 ) <= (others=>'1'); 01217 01218 01219 gen_mode2: if( trd4_mode=0 ) generate 01220 01221 pr_main_mode2: process( clk ) begin 01222 if( rising_edge( clk ) ) then 01223 if( reset='0' ) then 01224 main_mode2_4 <= '0' after 1 ns; 01225 elsif( bl_cmd_data_we1(0)='1' and cmd0_adr( 9 downto 8 )="00" and cmd0_adr( 4 downto 0 )="01010" ) then 01226 main_mode2_4 <= data2(4) after 1 ns; 01227 end if; 01228 end if; 01229 end process; 01230 01231 end generate; 01232 01233 gen_dmar2: if( trd4_mode=2 ) generate 01234 01235 main_mode2_4 <= not trd_drq(4).en; 01236 01237 end generate; 01238 01239 01240 end pb_adm_ctrl_m2;
1.7.4