Граф наследования:pb_adm_ctrl_m2:
Architectures | |
| pb_adm_ctrl_m2 | Architecture |
Libraries | |
| IEEE | |
| ieee | |
| unisim | |
| work | |
Packages | |
| STD_LOGIC_1164 | |
| std_logic_arith | |
| vital_timing | |
| VCOMPONENTS | |
| adm2_pkg | Package <adm2_pkg> |
Generics | |
| trd1_in | in integer := 0 |
| trd2_in | in integer := 0 |
| trd3_in | in integer := 0 |
| trd4_in | in integer := 0 |
| trd5_in | in integer := 0 |
| trd6_in | in integer := 0 |
| trd7_in | in integer := 0 |
| trd1_st | in integer := 0 |
| trd2_st | in integer := 0 |
| trd3_st | in integer := 0 |
| trd4_st | in integer := 0 |
| trd5_st | in integer := 0 |
| trd6_st | in integer := 0 |
| trd7_st | in integer := 0 |
| rom0 | in bl_trd_rom |
| rom1 | in bl_trd_rom |
| rom2 | in bl_trd_rom |
| rom3 | in bl_trd_rom |
| rom4 | in bl_trd_rom |
| rom5 | in bl_trd_rom |
| rom6 | in bl_trd_rom |
| rom7 | in bl_trd_rom |
| trd4_mode | in integer := 0 |
Ports | |
| reset | in std_logic |
| clk | in std_logic |
| lc_adr | in std_logic_vector ( 6 downto 0 ) |
| lc_host_data | in std_logic_vector ( 63 downto 0 ) |
| lc_data | out std_logic_vector ( 63 downto 0 ) |
| lc_wr | in std_logic |
| lc_rd | in std_logic |
| test_mode | in std_logic |
| trd_host_adr | out std_logic_vector ( 6 downto 0 ) |
| trd_host_data | out std_logic_vector ( 63 downto 0 ) |
| trd4_host_data | out std_logic_vector ( 63 downto 0 ) |
| trd_host_cmd | out std_logic_array_16xbl_cmd |
| trd_data | in std_logic_array_16x64 := ( others = > ( others = > ' 0 ' ) ) |
| trd_cmd_data | in std_logic_array_16x16 := ( others = > ( others = > ' 0 ' ) ) |
| trd_reset_fifo | in std_logic_array_16xbl_reset_fifo := ( others = > ' 0 ' ) |
| trd_drq | in std_logic_array_16xbl_drq := ( others = > ( others = > ' 0 ' ) ) |
| int1 | in std_logic := ' 0 ' |
| drq0 | in bl_drq := ( ' 0 ' , ' 0 ' , ' 0 ' ) |
| drq1 | in bl_drq := ( ' 0 ' , ' 0 ' , ' 0 ' ) |
| drq2 | in bl_drq := ( ' 0 ' , ' 0 ' , ' 0 ' ) |
| drq3 | in bl_drq := ( ' 0 ' , ' 0 ' , ' 0 ' ) |
| irq1 | out std_logic |
| dmar0 | out std_logic |
| dmar1 | out std_logic |
| dmar2 | out std_logic |
| dmar3 | out std_logic |
Подробное описание
См. определение в файле pb_adm_ctrl_m2.vhd строка 151
Объявления и описания членов класса находятся в файле:
- adm/cl_ambpex5/rtl/pb_adm_ctrl_m2.vhd
