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AMBPEX5_v20_SX50T_CORE
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00001 --------------------------------------------------------------------------------------------------- 00002 -- 00003 -- Title : trd_main_v8 00004 -- Author : Dmitry Smekhov 00005 -- Company : Instrumental System 00006 -- 00007 -- Version : 1.4 00008 -- 00009 --------------------------------------------------------------------------------------------------- 00010 -- 00011 -- Description : Реализация тетрады MAIN 00012 -- 00013 -- Модификация 8 - не используются счётчики CNT0, CNT1, CNT2 00014 -- Выход cmd_data_out реализован на мультиплексоре 00015 -- Узел начального тестирования сбрасывается через сигнал сброса FIFO 00016 -- Поддерживается тестовый режим работы SYNX 00017 -- 00018 --------------------------------------------------------------------------------------------------- 00019 -- 00020 -- Регистр SYNX 00021 -- 0 - RDY0_OUT 00022 -- 1 - RDY1_OUT 00023 -- 4 - RDY0_OE 00024 -- 5 - RDY1_OE 00025 -- 12 - START_EN_OUT 00026 -- 13 - SYNC0_OUT 00027 -- 14 - ENCODE_OUT 00028 -- 15 - SYNX_TEST_MODE 00029 -- 00030 -- Регистр SYNX_IN - адрес 0x202 00031 -- 9 - SN_RDY0 00032 -- 10 - SN_RDY1 00033 -- 11 - SN_START 00034 -- 12 - SN_START_EN 00035 -- 13 - SN_SYNC0 00036 -- 14 - SN_ENCODE - вход тактовой частоы 00037 -- 15 - SYNX_TEST_MODE - значение установленное в SYNX_TEST_MODE 00038 -- 00039 --------------------------------------------------------------------------------------------------- 00040 -- 00041 -- Version 1.4 10.06.2010 00042 -- Добавлены входы irq и drq для тетрад 8..15 00043 -- Входы начинают действовать при установке параметра ext_drq=1 00044 -- 00045 -- Добавлен регистр TEST_MODE - управление режимом формирования 00046 -- тестовой последовательности 00047 -- 00048 -- 00049 --------------------------------------------------------------------------------------------------- 00050 -- 00051 -- Version 1.3 26.03.2009 00052 -- Добавлен выход запроса DMA 00053 -- 00054 -- 11.05.2010 Добавлены триггеры на выходы reset_out, fifo_rst_out 00055 -- 00056 --------------------------------------------------------------------------------------------------- 00057 -- 00058 -- Version 1.2 06.12.2006 00059 -- Исправлено формирование запроса DMA - запрос разрешается при установке MODE0[3]=1 00060 -- Исправлен сброс тестового регистра - сброс может производиться через команду сброса FIFO 00061 -- 00062 --------------------------------------------------------------------------------------------------- 00063 -- 00064 -- Version 1.1 12.12.2005 00065 -- Убран буфер с 3-состоянием 00066 -- 00067 --------------------------------------------------------------------------------------------------- 00068 -- 00069 -- Version 1.0 25.08.2005 00070 -- Создан из trd_main_v1 версии 1.2 00071 -- 00072 --------------------------------------------------------------------------------------------------- 00073 00074 00075 library IEEE; 00076 use IEEE.STD_LOGIC_1164.all; 00077 00078 use work.adm2_pkg.all; 00079 00080 package trd_main_v8_pkg is 00081 00082 constant ID_MAIN : std_logic_vector( 15 downto 0 ):=x"0001"; -- идентификатор тетрады 00083 constant ID_MODE_MAIN : std_logic_vector( 15 downto 0 ):=x"0008"; -- модификатор тетрады 00084 constant VER_MAIN : std_logic_vector( 15 downto 0 ):=x"0104"; -- версия тетрады 00085 constant RES_MAIN : std_logic_vector( 15 downto 0 ):=x"0010"; -- ресурсы тетрады 00086 constant FIFO_MAIN : std_logic_vector( 15 downto 0 ):=x"0100"; -- размер FIFO 00087 constant FTYPE_MAIN : std_logic_vector( 15 downto 0 ):=x"0040"; -- ширина FIFO 00088 00089 component trd_main_v8 is 00090 generic( 00091 sync0_mode : in integer:=0; -- режим управления sync0_out 00092 -- 0 - через SYNX(13) 00093 -- 1 - при SYNX(15)='0' - вход sn_sync0_in 00094 -- при SYNX(15)='1' - через SYNX(13) 00095 00096 ext_drq : in integer:=0 -- 0 - используются только входы b1_drq - b7_drq 00097 -- 1 - используются все входы b_drq 00098 ); 00099 port ( 00100 00101 -- GLOBAL 00102 reset : in std_logic; 00103 clk : in std_logic; 00104 00105 -- T0 00106 adr_in : in std_logic_vector( 6 downto 0 ); -- шина адреса 00107 data_in : in std_logic_vector( 63 downto 0 ); -- шина данных для DATA 00108 cmd_data_in : in std_logic_vector( 15 downto 0 ); -- шина данных для CMD_DATA 00109 00110 cmd : in bl_cmd; -- команда для терады 00111 00112 data_out : out std_logic_vector( 63 downto 0 ); -- выход DATA 00113 cmd_data_out: out std_logic_vector( 15 downto 0 ); -- выход регистров 00114 00115 bx_drq : out bl_drq; -- управление DMA 00116 00117 test_mode : out std_logic; -- 1 - тестовый режим работы 00118 test_mode_init: in std_logic:='1'; -- начальное состояние test_mode 00119 fifo_rst_out: out std_logic; -- 0 - сброс FIFO 00120 00121 -- Вход прерываний 00122 b1_irq : in std_logic:='0'; 00123 b2_irq : in std_logic:='0'; 00124 b3_irq : in std_logic:='0'; 00125 b4_irq : in std_logic:='0'; 00126 b5_irq : in std_logic:='0'; 00127 b6_irq : in std_logic:='0'; 00128 b7_irq : in std_logic:='0'; 00129 b8_irq : in std_logic:='0'; 00130 b9_irq : in std_logic:='0'; 00131 b10_irq : in std_logic:='0'; 00132 b11_irq : in std_logic:='0'; 00133 b12_irq : in std_logic:='0'; 00134 b13_irq : in std_logic:='0'; 00135 b14_irq : in std_logic:='0'; 00136 b15_irq : in std_logic:='0'; 00137 00138 00139 -- Вход запросов DMA 00140 b1_drq : in bl_drq:=( '0', '0', '0' ); 00141 b2_drq : in bl_drq:=( '0', '0', '0' ); 00142 b3_drq : in bl_drq:=( '0', '0', '0' ); 00143 b4_drq : in bl_drq:=( '0', '0', '0' ); 00144 b5_drq : in bl_drq:=( '0', '0', '0' ); 00145 b6_drq : in bl_drq:=( '0', '0', '0' ); 00146 b7_drq : in bl_drq:=( '0', '0', '0' ); 00147 b8_drq : in bl_drq:=( '0', '0', '0' ); 00148 b9_drq : in bl_drq:=( '0', '0', '0' ); 00149 b10_drq : in bl_drq:=( '0', '0', '0' ); 00150 b11_drq : in bl_drq:=( '0', '0', '0' ); 00151 b12_drq : in bl_drq:=( '0', '0', '0' ); 00152 b13_drq : in bl_drq:=( '0', '0', '0' ); 00153 b14_drq : in bl_drq:=( '0', '0', '0' ); 00154 b15_drq : in bl_drq:=( '0', '0', '0' ); 00155 00156 -- Выход DRQ и IRQ 00157 int1 : out std_logic; 00158 int2 : out std_logic; 00159 int3 : out std_logic; 00160 00161 drq0 : out bl_drq; 00162 drq1 : out bl_drq; 00163 drq2 : out bl_drq; 00164 drq3 : out bl_drq; 00165 00166 00167 reset_out : out std_logic; -- программный сброс 00168 00169 00170 -- Управление мультплексором 00171 cp0 : out std_logic; 00172 cp1 : out std_logic; 00173 00174 -- Управление генераторами 00175 goe0 : out std_logic; 00176 goe1 : out std_logic; 00177 00178 -- THDAC 00179 thclk : out std_logic; -- тактовая частота загрузки ИПН 00180 thdin : out std_logic; -- данные ИПН 00181 thrs : out std_logic; -- сброс ИПН 00182 thld : out std_logic; -- загрузка данных в ИПН 00183 00184 00185 00186 mode0 : out std_logic_vector( 15 downto 0 ); -- регистр MODE0 00187 mode1 : out std_logic_vector( 15 downto 0 ); -- регистр MODE1 00188 synx : out std_logic_vector( 15 downto 0 ); -- регистр SYNX 00189 00190 -- Выход регистров выбора канала DMA 00191 sel_drq0 : out std_logic_vector( 6 downto 0 ); 00192 sel_drq1 : out std_logic_vector( 6 downto 0 ); 00193 sel_drq2 : out std_logic_vector( 6 downto 0 ); 00194 sel_drq3 : out std_logic_vector( 6 downto 0 ); 00195 00196 -- Тактовая частота 00197 b_clk : in std_logic_vector( 15 downto 0 ); -- вход 00198 bx_clk : out std_logic; -- выбранная тактовая частота тетрады 00199 00200 -- Старт 00201 b_start : in std_logic_vector( 15 downto 0 ); -- вход 00202 bx_start : out std_logic; -- сигнал разрешения сбора 00203 bx_start_a : out std_logic; -- асинхронный сигнал разрешения сбора 00204 bx_start_sync: out std_logic; -- импульс синхронизации 00205 00206 -- SYNX 00207 sn_rdy0 : in std_logic; -- готовность 0 00208 sn_rdy1 : in std_logic; -- готовность 1 00209 sn_start_en : in std_logic; -- 0 - разрешение сбора 00210 sn_sync0 : in std_logic; -- вход сигнала sync 00211 00212 sn_rdy0_out : out std_logic; -- выход sn_rdy0 00213 sn_rdy1_out : out std_logic; -- выход sn_rdy1 00214 sn_start_en_out: out std_logic; -- выход sn_start_en 00215 sn_sync0_out: out std_logic; -- выход sn_sync0 00216 sn_sync0_in : in std_logic:='0'; -- управление сигналом sn_syn0_out в ребочем режиме 00217 00218 sn_rdy0_oe : out std_logic; -- 1 - разрешение выхода sn_rdy0 00219 sn_rdy1_oe : out std_logic; -- 1 - разрешение выхода sn_rdy1 00220 sn_master : out std_logic -- 1 - разрешение выхода start_en, start, encode 00221 00222 00223 00224 ); 00225 end component; 00226 00227 end trd_main_v8_pkg; 00228 00229 00230 00231 library ieee; 00232 use ieee.std_logic_1164.all; 00233 00234 library work; 00235 use work.adm2_pkg.all; 00236 use work.ctrl_start_v2_pkg.all; 00237 use work.cl_test0_v4_pkg.all; 00238 00239 entity trd_main_v8 is 00240 generic( 00241 sync0_mode : in integer:=0; -- режим управления sync0_out 00242 -- 0 - через SYNX(13) 00243 -- 1 - при SYNX(15)='0' - вход sn_sync0_in 00244 -- при SYNX(15)='1' - через SYNX(13) 00245 00246 ext_drq : in integer:=0 -- 0 - используются только входы b1_drq - b7_drq 00247 -- 1 - используются все входы b_drq 00248 00249 ); 00250 port ( 00251 -- GLOBAL 00252 reset : in std_logic; 00253 clk : in std_logic; 00254 00255 -- T0 00256 adr_in : in std_logic_vector( 6 downto 0 ); -- шина адреса 00257 data_in : in std_logic_vector( 63 downto 0 ); -- шина данных для DATA 00258 cmd_data_in : in std_logic_vector( 15 downto 0 ); -- шина данных для CMD_DATA 00259 00260 cmd : in bl_cmd; -- команда для терады 00261 00262 data_out : out std_logic_vector( 63 downto 0 ); -- выход DATA 00263 cmd_data_out: out std_logic_vector( 15 downto 0 ); -- выход регистров 00264 00265 bx_drq : out bl_drq; -- управление DMA 00266 00267 test_mode : out std_logic; -- 1 - тестовый режим работы 00268 test_mode_init: in std_logic:='1'; -- начальное состояние test_mode 00269 fifo_rst_out: out std_logic; -- 0 - сброс FIFO 00270 00271 -- Вход прерываний 00272 b1_irq : in std_logic:='0'; 00273 b2_irq : in std_logic:='0'; 00274 b3_irq : in std_logic:='0'; 00275 b4_irq : in std_logic:='0'; 00276 b5_irq : in std_logic:='0'; 00277 b6_irq : in std_logic:='0'; 00278 b7_irq : in std_logic:='0'; 00279 b8_irq : in std_logic:='0'; 00280 b9_irq : in std_logic:='0'; 00281 b10_irq : in std_logic:='0'; 00282 b11_irq : in std_logic:='0'; 00283 b12_irq : in std_logic:='0'; 00284 b13_irq : in std_logic:='0'; 00285 b14_irq : in std_logic:='0'; 00286 b15_irq : in std_logic:='0'; 00287 00288 -- Вход запросов DMA 00289 b1_drq : in bl_drq:=( '0', '0', '0' ); 00290 b2_drq : in bl_drq:=( '0', '0', '0' ); 00291 b3_drq : in bl_drq:=( '0', '0', '0' ); 00292 b4_drq : in bl_drq:=( '0', '0', '0' ); 00293 b5_drq : in bl_drq:=( '0', '0', '0' ); 00294 b6_drq : in bl_drq:=( '0', '0', '0' ); 00295 b7_drq : in bl_drq:=( '0', '0', '0' ); 00296 b8_drq : in bl_drq:=( '0', '0', '0' ); 00297 b9_drq : in bl_drq:=( '0', '0', '0' ); 00298 b10_drq : in bl_drq:=( '0', '0', '0' ); 00299 b11_drq : in bl_drq:=( '0', '0', '0' ); 00300 b12_drq : in bl_drq:=( '0', '0', '0' ); 00301 b13_drq : in bl_drq:=( '0', '0', '0' ); 00302 b14_drq : in bl_drq:=( '0', '0', '0' ); 00303 b15_drq : in bl_drq:=( '0', '0', '0' ); 00304 00305 -- Выход DRQ и IRQ 00306 int1 : out std_logic; 00307 int2 : out std_logic; 00308 int3 : out std_logic; 00309 00310 drq0 : out bl_drq; 00311 drq1 : out bl_drq; 00312 drq2 : out bl_drq; 00313 drq3 : out bl_drq; 00314 00315 00316 reset_out : out std_logic; -- программный сброс 00317 00318 00319 -- Управление мультплексором 00320 cp0 : out std_logic; 00321 cp1 : out std_logic; 00322 00323 -- Управление генераторами 00324 goe0 : out std_logic; 00325 goe1 : out std_logic; 00326 00327 -- THDAC 00328 thclk : out std_logic; -- тактовая частота загрузки ИПН 00329 thdin : out std_logic; -- данные ИПН 00330 thrs : out std_logic; -- сброс ИПН 00331 thld : out std_logic; -- загрузка данных в ИПН 00332 00333 00334 00335 mode0 : out std_logic_vector( 15 downto 0 ); -- регистр MODE0 00336 mode1 : out std_logic_vector( 15 downto 0 ); -- регистр MODE1 00337 synx : out std_logic_vector( 15 downto 0 ); -- регистр SYNX 00338 00339 -- Выход регистров выбора канала DMA 00340 sel_drq0 : out std_logic_vector( 6 downto 0 ); 00341 sel_drq1 : out std_logic_vector( 6 downto 0 ); 00342 sel_drq2 : out std_logic_vector( 6 downto 0 ); 00343 sel_drq3 : out std_logic_vector( 6 downto 0 ); 00344 00345 -- Тактовая частота 00346 b_clk : in std_logic_vector( 15 downto 0 ); -- вход 00347 bx_clk : out std_logic; -- выбранная тактовая частота тетрады 00348 00349 -- Старт 00350 b_start : in std_logic_vector( 15 downto 0 ); -- вход 00351 bx_start : out std_logic; -- сигнал разрешения сбора 00352 bx_start_a : out std_logic; -- асинхронный сигнал разрешения сбора 00353 bx_start_sync: out std_logic; -- импульс синхронизации 00354 00355 -- SYNX 00356 sn_rdy0 : in std_logic; -- готовность 0 00357 sn_rdy1 : in std_logic; -- готовность 1 00358 sn_start_en : in std_logic; -- 0 - разрешение сбора 00359 sn_sync0 : in std_logic; -- вход сигнала sync 00360 00361 sn_rdy0_out : out std_logic; -- выход sn_rdy0 00362 sn_rdy1_out : out std_logic; -- выход sn_rdy1 00363 sn_start_en_out: out std_logic; -- выход sn_start_en 00364 sn_sync0_out: out std_logic; -- выход sn_sync0 00365 sn_sync0_in : in std_logic:='0'; -- управление сигналом sn_syn0_out в ребочем режиме 00366 00367 sn_rdy0_oe : out std_logic; -- 1 - разрешение выхода sn_rdy0 00368 sn_rdy1_oe : out std_logic; -- 1 - разрешение выхода sn_rdy1 00369 sn_master : out std_logic -- 1 - разрешение выхода start_en, start, encode 00370 00371 00372 00373 ); 00374 00375 00376 end trd_main_v8; 00377 00378 00379 architecture trd_main_v8 of trd_main_v8 is 00380 00381 component cl_test0_v1 is 00382 port( 00383 reset: in std_logic; 00384 clk: in std_logic; 00385 00386 adr_in: in std_logic_vector( 6 downto 0 ); 00387 data_in: in std_logic_vector( 63 downto 0 ); 00388 data_en: in std_logic; 00389 data_cs: in std_logic; 00390 00391 data_out: out std_logic_vector( 63 downto 0 ); 00392 test_mode_init: in std_logic; 00393 test_mode: out std_logic 00394 ); 00395 00396 end component; 00397 00398 component ctrl_thdac is 00399 port( 00400 reset : in std_logic; -- 0 - сброс 00401 clk : in std_logic; -- тактовая частота 100mhz 00402 start : in std_logic; -- 1 - страт 00403 data_dac : in std_logic_vector(11 downto 0); -- данные для ипн 00404 clkdac_out : out std_logic; -- выходная тактовая частота 00405 ld : out std_logic; -- сигнал загрузки ипн 00406 ready : out std_logic; -- 1 - пересылка завершена 00407 thrs : out std_logic; -- 0 - сброс ипн 00408 sdo_dac : out std_logic -- последовательный порта ипн 00409 ); 00410 end component; 00411 00412 00413 signal c_mode0 : std_logic_vector( 15 downto 0 ); -- MODE0 00414 signal c_mask, c_inv : std_logic_vector( 15 downto 0 ); -- IRQ_MAK, IRQ_INV 00415 signal c_thdac : std_logic_vector( 11 downto 0 ); -- THDAC 00416 signal thdac_start : std_logic; -- 1 - запуск выдачи в ИПН 00417 signal c_mux : std_logic_vector( 1 downto 0 ); -- MUX 00418 signal do : std_logic_vector( 63 downto 0 ); -- выход шины данных модуля тестирования 00419 signal c_synx : std_logic_vector( 15 downto 0 ); -- SYNX 00420 signal c_fmode : std_logic_vector( 5 downto 0 ); -- FMODE 00421 signal c_fdiv : std_logic_vector( 15 downto 0 ); -- FDIV 00422 signal fdiv_we : std_logic; -- 1 - запись в FDIV 00423 signal c_stmode : std_logic_vector( 15 downto 0 ); -- STMODE 00424 signal irq_en : std_logic_vector( 15 downto 0 ); -- IRQ_EN 00425 signal c_test_mode : std_logic; -- TEST_MODE 00426 00427 -- выбор канала прерывания 00428 signal c_sel0, c_sel1, c_sel2, c_sel3, c_sel4, c_sel5, c_sel6, c_sel7: std_logic_vector( 1 downto 0 ); 00429 00430 -- выбор канала запроса DMA 00431 signal c_sel_drq0, c_sel_drq1, c_sel_drq2, c_sel_drq3: std_logic_vector( 6 downto 0 ); 00432 signal b0_irq : std_logic; -- запрос прерывание 00433 signal b0_drq : bl_drq; -- запрос DMA 00434 signal rst : std_logic; -- 0 - сброс 00435 00436 -- распределение прерываний 00437 signal i0_1, i1_1, i2_1, i3_1, i4_1, i5_1, i6_1, i7_1 : std_logic; 00438 signal i0_2, i1_2, i2_2, i3_2, i4_2, i5_2, i6_2, i7_2 : std_logic; 00439 signal i0_3, i1_3, i2_3, i3_3, i4_3, i5_3, i6_3, i7_3 : std_logic; 00440 signal i8_1, i9_1, i10_1, i11_1, i12_1, i13_1, i14_1, i15_1 : std_logic; 00441 signal i8_2, i9_2, i10_2, i11_2, i12_2, i13_2, i14_2, i15_2 : std_logic; 00442 signal i8_3, i9_3, i10_3, i11_3, i12_3, i13_3, i14_3, i15_3 : std_logic; 00443 00444 signal status : std_logic_vector( 15 downto 0 ); -- регистр состояния 00445 signal th_rdy : std_logic; -- 1 - готовность ИПН 00446 signal data_csp : std_logic; -- 1 - чтение регистра DATA 00447 signal drq0i, drq1i, drq2i, drq3i: bl_drq; -- внутренние сигналы DMA 00448 00449 signal fifo_rst : std_logic; -- 0 - сброс узла тестирования 00450 signal synx_test_mode : std_logic; -- 1 - режим тестирования разъёма SYNX 00451 signal reg_synx_in : std_logic_vector( 15 downto 0 ); -- регистр SYNX_IN 00452 signal bx_clki : std_logic; 00453 00454 begin 00455 00456 00457 data_csp <= not cmd.data_cs; 00458 00459 d_test0: cl_test0_v4 00460 port map ( 00461 reset => reset, 00462 reset_reg => fifo_rst, 00463 clk => clk , 00464 reg_test_mode => c_test_mode, -- 1 - формирование псевдослучайной последовательности 00465 00466 adr_in => adr_in, 00467 data_in => data_in , 00468 data_en => cmd.data_we, 00469 --data_en => '0', 00470 data_cs => data_csp, 00471 00472 data_out => do , 00473 test_mode_init => test_mode_init, 00474 test_mode => test_mode); 00475 00476 00477 --xstatus: ctrl_buft16 port map( 00478 -- t => cmd.status_cs, 00479 -- i => status, 00480 -- o => cmd_data_out ); 00481 -- 00482 --xirq: ctrl_buft16 port map( 00483 -- t => cmd.cmd_data_cs, 00484 -- i => irq_en, 00485 -- o => cmd_data_out ); 00486 00487 00488 cmd_data_out <= status when cmd.status_cs='0' else 00489 irq_en when cmd.adr(1)='0' else 00490 reg_synx_in; 00491 00492 00493 00494 data_out<=do; 00495 00496 00497 irq_en(0)<='0'; 00498 irq_en( 15 downto 4 )<=(others=>'0'); 00499 00500 00501 pr_mode0: process( reset, clk ) 00502 variable vthdac_start: std_logic; 00503 variable vfdiv_we: std_logic; 00504 begin 00505 if( reset='0' ) then 00506 c_mode0<=(others=>'0'); 00507 elsif( rising_edge( clk ) ) then 00508 vthdac_start:='0'; 00509 vfdiv_we:='0'; 00510 if( cmd.cmd_data_we='1' ) then 00511 00512 if( cmd.adr(9)='0' and cmd.adr(8)='0' ) then 00513 case cmd.adr( 4 downto 0 ) is 00514 when "00000" => -- MODE0 00515 c_mode0<=cmd_data_in( 15 downto 0 ); 00516 when others=>null; 00517 end case; 00518 end if; 00519 end if; 00520 end if; 00521 end process; 00522 00523 00524 pr_reg: process( rst, clk ) 00525 variable vthdac_start: std_logic; 00526 variable vfdiv_we: std_logic; 00527 begin 00528 if( rst='0' ) then 00529 vthdac_start:='0'; 00530 vfdiv_we:='0'; 00531 irq_en( 3 downto 1 ) <= (others=>'0'); 00532 c_mask<=(others=>'0'); 00533 c_inv<=(others=>'0'); 00534 c_fmode<=(others=>'0'); 00535 c_fdiv<=(others=>'0'); 00536 c_stmode<=(others=>'0'); 00537 c_sel0<=(others=>'0'); 00538 c_sel1<=(others=>'0'); 00539 c_sel2<=(others=>'0'); 00540 c_sel3<=(others=>'0'); 00541 c_sel4<=(others=>'0'); 00542 c_sel5<=(others=>'0'); 00543 c_sel6<=(others=>'0'); 00544 c_sel7<=(others=>'0'); 00545 c_sel_drq0<=(others=>'0'); 00546 c_sel_drq1<=(others=>'0'); 00547 c_sel_drq2<=(others=>'0'); 00548 c_sel_drq3<=(others=>'0'); 00549 mode1<=(others=>'0'); 00550 c_synx<=(others=>'0'); 00551 c_mux<=(others=>'0'); 00552 c_thdac<=(others=>'0'); 00553 c_test_mode <= '0'; 00554 elsif( rising_edge( clk ) ) then 00555 vthdac_start:='0'; 00556 vfdiv_we:='0'; 00557 if( cmd.cmd_data_we='1' ) then 00558 if( cmd.adr(9)='1' and cmd.adr(8)='0' ) then 00559 if( cmd.adr(0)='0' ) then -- IRQENST 00560 irq_en( 3 downto 1 ) <= irq_en( 3 downto 1 ) or cmd_data_in( 3 downto 1 ); 00561 else 00562 irq_en( 3 downto 1 ) <= irq_en( 3 downto 1 ) and not cmd_data_in( 3 downto 1 ); 00563 end if; 00564 --irq_en( 3 downto 1 ) <= irq_en( 3 downto 1 ) or data_in( 3 downto 1 ); 00565 end if; 00566 00567 if( cmd.adr(9)='0' and cmd.adr(8)='0' ) then 00568 case cmd.adr( 4 downto 0 ) is 00569 when "00001" => -- C_MASK 00570 c_mask<=cmd_data_in( 15 downto 0 ); 00571 when "00010" => -- C_INV 00572 c_inv<=cmd_data_in( 15 downto 0 ); 00573 -- when "0001" => -- IRQ_ACK 00574 -- irq_ack<=data_in( 2 downto 0 ); 00575 when "00011" => -- FMODE 00576 c_fmode<=cmd_data_in( 5 downto 0 ); 00577 when "00100" => -- FDIV 00578 c_fdiv<=cmd_data_in( 15 downto 0 ); 00579 vfdiv_we:='1'; 00580 when "00101" => -- STMODE 00581 c_stmode<=cmd_data_in( 15 downto 0 ); 00582 00583 when "01001" => -- MODE1 00584 mode1 <= cmd_data_in( 15 downto 0 ); 00585 00586 when "01100" => -- TEST_MODE 00587 c_test_mode <= cmd_data_in(0); 00588 00589 when "01101" => -- SYNX 00590 c_synx( 15 downto 0 ) <=cmd_data_in( 15 downto 0 ); 00591 when "01110" => -- THDAC 00592 c_thdac<=cmd_data_in( 11 downto 0 ); 00593 vthdac_start:='1'; 00594 when "01111" => -- MUX 00595 c_mux<=cmd_data_in( 1 downto 0 ); 00596 when "10000" => -- c_sel0 00597 c_sel0( 1 downto 0 ) <=cmd_data_in( 1 downto 0 ); 00598 c_sel_drq0( 6 downto 0 ) <= cmd_data_in( 14 downto 8 ); 00599 when "10001" => -- c_sel1 00600 c_sel1( 1 downto 0 ) <=cmd_data_in( 1 downto 0 ); 00601 c_sel_drq1( 6 downto 0 ) <= cmd_data_in( 14 downto 8 ); 00602 when "10010" => -- c_sel2 00603 c_sel2( 1 downto 0 ) <=cmd_data_in( 1 downto 0 ); 00604 c_sel_drq2( 6 downto 0 ) <= cmd_data_in( 14 downto 8 ); 00605 when "10011" => -- c_sel3 00606 c_sel3( 1 downto 0 ) <=cmd_data_in( 1 downto 0 ); 00607 c_sel_drq3( 6 downto 0 ) <= cmd_data_in( 14 downto 8 ); 00608 when "10100" => -- c_sel4 00609 c_sel4( 1 downto 0 ) <=cmd_data_in( 1 downto 0 ); 00610 when "10101" => -- c_sel5 00611 c_sel5( 1 downto 0 ) <=cmd_data_in( 1 downto 0 ); 00612 when "10110" => -- c_sel6 00613 c_sel6( 1 downto 0 ) <=cmd_data_in( 1 downto 0 ); 00614 when "10111" => -- c_sel7 00615 c_sel7( 1 downto 0 ) <=cmd_data_in( 1 downto 0 ); 00616 00617 00618 when others=>null; 00619 end case; 00620 end if; 00621 end if; 00622 thdac_start <= vthdac_start; 00623 fdiv_we <= vfdiv_we; 00624 end if; 00625 end process; 00626 00627 rst<='0' when reset='0' or c_mode0(0)='1' else '1'; 00628 reset_out<=rst after 1 ns when rising_edge( clk ); 00629 00630 fifo_rst <= '0' when rst='0' or c_mode0(1)='1' else '1'; 00631 fifo_rst_out <= fifo_rst after 1 ns when rising_edge( clk ); 00632 00633 cp0<=c_mux(0); 00634 cp1<=c_mux(1); 00635 00636 -- Формирование прерываний 00637 i0_1<='1' when c_sel0(1 downto 0)="01" and b0_irq='1' else '0'; 00638 i1_1<='1' when c_sel1(1 downto 0)="01" and b1_irq='1' else '0'; 00639 i2_1<='1' when c_sel2(1 downto 0)="01" and b2_irq='1' else '0'; 00640 i3_1<='1' when c_sel3(1 downto 0)="01" and b3_irq='1' else '0'; 00641 i4_1<='1' when c_sel4(1 downto 0)="01" and b4_irq='1' else '0'; 00642 i5_1<='1' when c_sel5(1 downto 0)="01" and b5_irq='1' else '0'; 00643 i6_1<='1' when c_sel6(1 downto 0)="01" and b6_irq='1' else '0'; 00644 i7_1<='1' when c_sel7(1 downto 0)="01" and b7_irq='1' else '0'; 00645 i8_1<='1' when c_sel0(1 downto 0)="01" and b8_irq='1' else '0'; 00646 i9_1<='1' when c_sel1(1 downto 0)="01" and b9_irq='1' else '0'; 00647 i10_1<='1' when c_sel2(1 downto 0)="01" and b10_irq='1' else '0'; 00648 i11_1<='1' when c_sel3(1 downto 0)="01" and b11_irq='1' else '0'; 00649 i12_1<='1' when c_sel4(1 downto 0)="01" and b12_irq='1' else '0'; 00650 i13_1<='1' when c_sel5(1 downto 0)="01" and b13_irq='1' else '0'; 00651 i14_1<='1' when c_sel6(1 downto 0)="01" and b14_irq='1' else '0'; 00652 i15_1<='1' when c_sel7(1 downto 0)="01" and b15_irq='1' else '0'; 00653 00654 i0_2<='1' when c_sel0(1 downto 0)="10" and b0_irq='1' else '0'; 00655 i1_2<='1' when c_sel1(1 downto 0)="10" and b1_irq='1' else '0'; 00656 i2_2<='1' when c_sel2(1 downto 0)="10" and b2_irq='1' else '0'; 00657 i3_2<='1' when c_sel3(1 downto 0)="10" and b3_irq='1' else '0'; 00658 i4_2<='1' when c_sel4(1 downto 0)="10" and b4_irq='1' else '0'; 00659 i5_2<='1' when c_sel5(1 downto 0)="10" and b5_irq='1' else '0'; 00660 i6_2<='1' when c_sel6(1 downto 0)="10" and b6_irq='1' else '0'; 00661 i7_2<='1' when c_sel7(1 downto 0)="10" and b7_irq='1' else '0'; 00662 i8_2<='1' when c_sel0(1 downto 0)="10" and b8_irq='1' else '0'; 00663 i9_2<='1' when c_sel1(1 downto 0)="10" and b9_irq='1' else '0'; 00664 i10_2<='1' when c_sel2(1 downto 0)="10" and b10_irq='1' else '0'; 00665 i11_2<='1' when c_sel3(1 downto 0)="10" and b11_irq='1' else '0'; 00666 i12_2<='1' when c_sel4(1 downto 0)="10" and b12_irq='1' else '0'; 00667 i13_2<='1' when c_sel5(1 downto 0)="10" and b13_irq='1' else '0'; 00668 i14_2<='1' when c_sel6(1 downto 0)="10" and b14_irq='1' else '0'; 00669 i15_2<='1' when c_sel7(1 downto 0)="10" and b15_irq='1' else '0'; 00670 00671 i0_3<='1' when c_sel0(1 downto 0)="11" and b0_irq='1' else '0'; 00672 i1_3<='1' when c_sel1(1 downto 0)="11" and b1_irq='1' else '0'; 00673 i2_3<='1' when c_sel2(1 downto 0)="11" and b2_irq='1' else '0'; 00674 i3_3<='1' when c_sel3(1 downto 0)="11" and b3_irq='1' else '0'; 00675 i4_3<='1' when c_sel4(1 downto 0)="11" and b4_irq='1' else '0'; 00676 i5_3<='1' when c_sel5(1 downto 0)="11" and b5_irq='1' else '0'; 00677 i6_3<='1' when c_sel6(1 downto 0)="11" and b6_irq='1' else '0'; 00678 i7_3<='1' when c_sel7(1 downto 0)="11" and b7_irq='1' else '0'; 00679 i8_3<='1' when c_sel0(1 downto 0)="11" and b8_irq='1' else '0'; 00680 i9_3<='1' when c_sel1(1 downto 0)="11" and b9_irq='1' else '0'; 00681 i10_3<='1' when c_sel2(1 downto 0)="11" and b10_irq='1' else '0'; 00682 i11_3<='1' when c_sel3(1 downto 0)="11" and b11_irq='1' else '0'; 00683 i12_3<='1' when c_sel4(1 downto 0)="11" and b12_irq='1' else '0'; 00684 i13_3<='1' when c_sel5(1 downto 0)="11" and b13_irq='1' else '0'; 00685 i14_3<='1' when c_sel6(1 downto 0)="11" and b14_irq='1' else '0'; 00686 i15_3<='1' when c_sel7(1 downto 0)="11" and b15_irq='1' else '0'; 00687 00688 int1<=( i0_1 or i1_1 or i2_1 or i3_1 or i4_1 or i5_1 or i6_1 or i7_1 or 00689 i8_1 or i9_1 or i10_1 or i11_1 or i12_1 or i13_1 or i14_1 or i15_1 00690 ) and ( irq_en(1) ); 00691 00692 int2<=( i0_2 or i1_2 or i2_2 or i3_2 or i4_2 or i5_2 or i6_2 or i7_2 or 00693 i8_2 or i9_2 or i10_2 or i11_2 or i12_2 or i13_2 or i14_2 or i15_2 00694 ) and ( irq_en(2) ); 00695 00696 int3<=( i0_3 or i1_3 or i2_3 or i3_3 or i4_3 or i5_3 or i6_3 or i7_3 or 00697 i8_3 or i9_3 or i10_3 or i11_3 or i12_3 or i13_3 or i14_3 or i15_3 00698 ) and ( irq_en(3) ); 00699 00700 00701 gen_trd0: if( ext_drq=0 ) generate 00702 00703 pr_drq0: process( c_sel_drq0, b0_drq, b1_drq, b2_drq, b3_drq, 00704 b4_drq, b5_drq, b6_drq, b7_drq ) is 00705 begin 00706 case c_sel_drq0( 2 downto 0 ) is 00707 when "000" => drq0i<=b0_drq; 00708 when "001" => drq0i<=b1_drq; 00709 when "010" => drq0i<=b2_drq; 00710 when "011" => drq0i<=b3_drq; 00711 when "100" => drq0i<=b4_drq; 00712 when "101" => drq0i<=b5_drq; 00713 when "110" => drq0i<=b6_drq; 00714 when "111" => drq0i<=b7_drq; 00715 when others => null; 00716 end case; 00717 end process; 00718 00719 drq0.en<=drq0i.en and c_sel_drq0(4); 00720 drq0.req<=drq0i.req; 00721 drq0.ack<=drq0i.ack; 00722 00723 pr_drq1: process( c_sel_drq1, b0_drq, b1_drq, b2_drq, b3_drq, 00724 b4_drq, b5_drq, b6_drq, b7_drq ) is 00725 begin 00726 case c_sel_drq1( 2 downto 0 ) is 00727 when "000" => drq1i<=b0_drq; 00728 when "001" => drq1i<=b1_drq; 00729 when "010" => drq1i<=b2_drq; 00730 when "011" => drq1i<=b3_drq; 00731 when "100" => drq1i<=b4_drq; 00732 when "101" => drq1i<=b5_drq; 00733 when "110" => drq1i<=b6_drq; 00734 when "111" => drq1i<=b7_drq; 00735 when others => null; 00736 end case; 00737 end process; 00738 00739 drq1.en<=drq1i.en and c_sel_drq1(4); 00740 drq1.req<=drq1i.req; 00741 drq1.ack<=drq1i.ack; 00742 00743 pr_drq2: process( c_sel_drq2, b0_drq, b1_drq, b2_drq, b3_drq, 00744 b4_drq, b5_drq, b6_drq, b7_drq ) is 00745 begin 00746 case c_sel_drq2( 2 downto 0 ) is 00747 when "000" => drq2i<=b0_drq; 00748 when "001" => drq2i<=b1_drq; 00749 when "010" => drq2i<=b2_drq; 00750 when "011" => drq2i<=b3_drq; 00751 when "100" => drq2i<=b4_drq; 00752 when "101" => drq2i<=b5_drq; 00753 when "110" => drq2i<=b6_drq; 00754 when "111" => drq2i<=b7_drq; 00755 when others => null; 00756 end case; 00757 end process; 00758 00759 drq2.en<=drq2i.en and c_sel_drq2(4); 00760 drq2.req<=drq2i.req; 00761 drq2.ack<=drq2i.ack; 00762 00763 00764 00765 00766 00767 pr_drq3: process( c_sel_drq3, b0_drq, b1_drq, b2_drq, b3_drq, 00768 b4_drq, b5_drq, b6_drq, b7_drq ) is 00769 begin 00770 case c_sel_drq3( 2 downto 0 ) is 00771 when "000" => drq3i<=b0_drq; 00772 when "001" => drq3i<=b1_drq; 00773 when "010" => drq3i<=b2_drq; 00774 when "011" => drq3i<=b3_drq; 00775 when "100" => drq3i<=b4_drq; 00776 when "101" => drq3i<=b5_drq; 00777 when "110" => drq3i<=b6_drq; 00778 when "111" => drq3i<=b7_drq; 00779 when others => null; 00780 end case; 00781 end process; 00782 00783 drq3.en<=drq3i.en and c_sel_drq3(4); 00784 drq3.req<=drq3i.req; 00785 drq3.ack<=drq3i.ack; 00786 00787 end generate; 00788 00789 00790 00791 gen_trd8: if( ext_drq=1 ) generate 00792 00793 drq0i <= b0_drq when c_sel_drq0( 3 downto 0 )="0000" else 00794 b1_drq when c_sel_drq0( 3 downto 0 )="0001" else 00795 b2_drq when c_sel_drq0( 3 downto 0 )="0010" else 00796 b3_drq when c_sel_drq0( 3 downto 0 )="0011" else 00797 b4_drq when c_sel_drq0( 3 downto 0 )="0100" else 00798 b5_drq when c_sel_drq0( 3 downto 0 )="0101" else 00799 b6_drq when c_sel_drq0( 3 downto 0 )="0110" else 00800 b7_drq when c_sel_drq0( 3 downto 0 )="0111" else 00801 b8_drq when c_sel_drq0( 3 downto 0 )="1000" else 00802 b9_drq when c_sel_drq0( 3 downto 0 )="1001" else 00803 b10_drq when c_sel_drq0( 3 downto 0 )="1010" else 00804 b11_drq when c_sel_drq0( 3 downto 0 )="1011" else 00805 b12_drq when c_sel_drq0( 3 downto 0 )="1100" else 00806 b13_drq when c_sel_drq0( 3 downto 0 )="1101" else 00807 b14_drq when c_sel_drq0( 3 downto 0 )="1110" else 00808 b15_drq when c_sel_drq0( 3 downto 0 )="1111"; 00809 00810 00811 drq0.en<=drq0i.en and c_sel_drq0(4); 00812 drq0.req<=drq0i.req; 00813 drq0.ack<=drq0i.ack; 00814 00815 drq1i <= b0_drq when c_sel_drq1( 3 downto 0 )="0000" else 00816 b1_drq when c_sel_drq1( 3 downto 0 )="0001" else 00817 b2_drq when c_sel_drq1( 3 downto 0 )="0010" else 00818 b3_drq when c_sel_drq1( 3 downto 0 )="0011" else 00819 b4_drq when c_sel_drq1( 3 downto 0 )="0100" else 00820 b5_drq when c_sel_drq1( 3 downto 0 )="0101" else 00821 b6_drq when c_sel_drq1( 3 downto 0 )="0110" else 00822 b7_drq when c_sel_drq1( 3 downto 0 )="0111" else 00823 b8_drq when c_sel_drq1( 3 downto 0 )="1000" else 00824 b9_drq when c_sel_drq1( 3 downto 0 )="1001" else 00825 b10_drq when c_sel_drq1( 3 downto 0 )="1010" else 00826 b11_drq when c_sel_drq1( 3 downto 0 )="1011" else 00827 b12_drq when c_sel_drq1( 3 downto 0 )="1100" else 00828 b13_drq when c_sel_drq1( 3 downto 0 )="1101" else 00829 b14_drq when c_sel_drq1( 3 downto 0 )="1110" else 00830 b15_drq when c_sel_drq1( 3 downto 0 )="1111"; 00831 00832 drq1.en<=drq1i.en and c_sel_drq1(4); 00833 drq1.req<=drq1i.req; 00834 drq1.ack<=drq1i.ack; 00835 00836 drq2i <= b0_drq when c_sel_drq2( 3 downto 0 )="0000" else 00837 b1_drq when c_sel_drq2( 3 downto 0 )="0001" else 00838 b2_drq when c_sel_drq2( 3 downto 0 )="0010" else 00839 b3_drq when c_sel_drq2( 3 downto 0 )="0011" else 00840 b4_drq when c_sel_drq2( 3 downto 0 )="0100" else 00841 b5_drq when c_sel_drq2( 3 downto 0 )="0101" else 00842 b6_drq when c_sel_drq2( 3 downto 0 )="0110" else 00843 b7_drq when c_sel_drq2( 3 downto 0 )="0111" else 00844 b8_drq when c_sel_drq2( 3 downto 0 )="1000" else 00845 b9_drq when c_sel_drq2( 3 downto 0 )="1001" else 00846 b10_drq when c_sel_drq2( 3 downto 0 )="1010" else 00847 b11_drq when c_sel_drq2( 3 downto 0 )="1011" else 00848 b12_drq when c_sel_drq2( 3 downto 0 )="1100" else 00849 b13_drq when c_sel_drq2( 3 downto 0 )="1101" else 00850 b14_drq when c_sel_drq2( 3 downto 0 )="1110" else 00851 b15_drq when c_sel_drq2( 3 downto 0 )="1111"; 00852 00853 drq2.en<=drq2i.en and c_sel_drq2(4); 00854 drq2.req<=drq2i.req; 00855 drq2.ack<=drq2i.ack; 00856 00857 00858 00859 00860 00861 drq3i <= b0_drq when c_sel_drq3( 3 downto 0 )="0000" else 00862 b1_drq when c_sel_drq3( 3 downto 0 )="0001" else 00863 b2_drq when c_sel_drq3( 3 downto 0 )="0010" else 00864 b3_drq when c_sel_drq3( 3 downto 0 )="0011" else 00865 b4_drq when c_sel_drq3( 3 downto 0 )="0100" else 00866 b5_drq when c_sel_drq3( 3 downto 0 )="0101" else 00867 b6_drq when c_sel_drq3( 3 downto 0 )="0110" else 00868 b7_drq when c_sel_drq3( 3 downto 0 )="0111" else 00869 b8_drq when c_sel_drq3( 3 downto 0 )="1000" else 00870 b9_drq when c_sel_drq3( 3 downto 0 )="1001" else 00871 b10_drq when c_sel_drq3( 3 downto 0 )="1010" else 00872 b11_drq when c_sel_drq3( 3 downto 0 )="1011" else 00873 b12_drq when c_sel_drq3( 3 downto 0 )="1100" else 00874 b13_drq when c_sel_drq3( 3 downto 0 )="1101" else 00875 b14_drq when c_sel_drq3( 3 downto 0 )="1110" else 00876 b15_drq when c_sel_drq3( 3 downto 0 )="1111"; 00877 00878 drq3.en<=drq3i.en and c_sel_drq3(4); 00879 drq3.req<=drq3i.req; 00880 drq3.ack<=drq3i.ack; 00881 00882 end generate; 00883 00884 00885 sel_drq0 <= c_sel_drq0; 00886 sel_drq1 <= c_sel_drq1; 00887 sel_drq2 <= c_sel_drq2; 00888 sel_drq3 <= c_sel_drq3; 00889 00890 mode0 <= c_mode0; 00891 00892 00893 00894 00895 00896 b0_drq.en<=c_mode0(3); 00897 b0_drq.req<= c_mode0(3); 00898 b0_drq.ack<=data_csp; 00899 00900 bx_drq <= b0_drq; 00901 00902 start: ctrl_start_v2 port map ( 00903 00904 reset => rst, 00905 mode0 => c_mode0 , 00906 stmode => c_stmode, 00907 fmode => c_fmode, 00908 fdiv => c_fdiv, 00909 fdiv_we => fdiv_we, 00910 00911 b_clk => b_clk, 00912 b_start => b_start, 00913 00914 bx_clk => bx_clki, 00915 bx_start => bx_start, 00916 bx_start_a => bx_start_a, 00917 bx_start_sync => bx_start_sync, 00918 goe0 => goe0, 00919 goe1 => goe1 00920 ); 00921 00922 00923 thdac: ctrl_thdac port map ( 00924 reset => rst, 00925 clk => clk, 00926 start => thdac_start, 00927 data_dac => c_thdac, 00928 clkDAC_out => thclk, 00929 ld => thld, 00930 ready => th_rdy, 00931 thrs => thrs, 00932 sdo_dac => thdin ); 00933 00934 -- STATUS 00935 status(0) <= th_rdy; -- CMD_RDY 00936 status(1) <= '1'; -- RDY 00937 status(2) <= '1'; -- EF 00938 status(3) <= '1'; -- PAE 00939 status(4) <= '0'; -- HF 00940 status(5) <= '1'; -- PAF 00941 status(6) <= '1'; -- FF 00942 status(7) <= '0'; -- OVR 00943 status(8) <= '0'; -- UND 00944 status(9) <= sn_rdy0; -- SN_RDY0 00945 status(10) <= sn_rdy1; -- SN_RDY1 00946 status(11) <= b_start(4); -- SN_START 00947 status(12) <= sn_start_en; -- SN_START_EN 00948 status(13) <= sn_sync0; -- SN_SYNC0 00949 status(14) <= b_start(1); -- COMP0 00950 status(15) <= b_start(2); -- COMP1 00951 00952 00953 pr_b0_irq: process( status, c_mask, c_inv, c_mode0 ) 00954 variable v: std_logic; 00955 begin 00956 v:='0'; 00957 if( c_mode0(2)='1' ) then 00958 for i in 0 to 15 loop 00959 if( ((status(i) xor c_inv(i)) and c_mask(i))='1' ) then 00960 v:='1'; 00961 end if; 00962 end loop; 00963 end if; 00964 b0_irq<=v; 00965 end process; 00966 00967 00968 sn_rdy0_out <= c_synx(0); 00969 sn_rdy1_out <= c_synx(1); 00970 sn_rdy0_oe <= c_synx(4); 00971 sn_rdy1_oe <= c_synx(5); 00972 sn_start_en_out <= c_synx(12); 00973 --sn_sync0_out <= c_synx(13); 00974 00975 synx_test_mode <= c_synx(15); 00976 00977 gen_syn0_0: if( sync0_mode=0 ) generate 00978 00979 sn_sync0_out <= c_synx(13); 00980 00981 end generate; 00982 00983 gen_syn0_1: if( sync0_mode=1 ) generate 00984 00985 sn_sync0_out <= sn_sync0_in when synx_test_mode='0' else c_synx(13); 00986 00987 end generate; 00988 00989 00990 bx_clk <= bx_clki when synx_test_mode='0' else c_synx(14); 00991 00992 sn_master <= c_mode0(4); 00993 00994 reg_synx_in( 8 downto 0 ) <= (others=>'0'); 00995 00996 reg_synx_in(9) <= sn_rdy0; -- SN_RDY0 00997 reg_synx_in(10) <= sn_rdy1; -- SN_RDY1 00998 reg_synx_in(11) <= b_start(4); -- SN_START 00999 reg_synx_in(12) <= sn_start_en; -- SN_START_EN 01000 reg_synx_in(13) <= sn_sync0; -- SN_SYNC0 01001 reg_synx_in(14) <= b_clk(4); -- SN_ENCODE 01002 reg_synx_in(15) <= synx_test_mode; -- SYNX_TEST_MODE 01003 01004 synx <= c_synx; 01005 01006 end trd_main_v8;
1.7.4