Граф наследования:trd_main_v8:
Architectures | |
| trd_main_v8 | Architecture |
Libraries | |
| ieee | |
| work | |
Packages | |
| std_logic_1164 | |
| adm2_pkg | Package <adm2_pkg> |
| ctrl_start_v2_pkg | Package <ctrl_start_v2_pkg> |
| cl_test0_v4_pkg | Package <cl_test0_v4_pkg> |
Generics | |
| sync0_mode | in integer := 0 |
| ext_drq | in integer := 0 |
Ports | |
| reset | in std_logic |
| clk | in std_logic |
| adr_in | in std_logic_vector ( 6 downto 0 ) |
| data_in | in std_logic_vector ( 63 downto 0 ) |
| cmd_data_in | in std_logic_vector ( 15 downto 0 ) |
| cmd | in bl_cmd |
| data_out | out std_logic_vector ( 63 downto 0 ) |
| cmd_data_out | out std_logic_vector ( 15 downto 0 ) |
| bx_drq | out bl_drq |
| test_mode | out std_logic |
| test_mode_init | in std_logic := ' 1 ' |
| fifo_rst_out | out std_logic |
| b1_irq | in std_logic := ' 0 ' |
| b2_irq | in std_logic := ' 0 ' |
| b3_irq | in std_logic := ' 0 ' |
| b4_irq | in std_logic := ' 0 ' |
| b5_irq | in std_logic := ' 0 ' |
| b6_irq | in std_logic := ' 0 ' |
| b7_irq | in std_logic := ' 0 ' |
| b8_irq | in std_logic := ' 0 ' |
| b9_irq | in std_logic := ' 0 ' |
| b10_irq | in std_logic := ' 0 ' |
| b11_irq | in std_logic := ' 0 ' |
| b12_irq | in std_logic := ' 0 ' |
| b13_irq | in std_logic := ' 0 ' |
| b14_irq | in std_logic := ' 0 ' |
| b15_irq | in std_logic := ' 0 ' |
| b1_drq | in bl_drq := ( ' 0 ' , ' 0 ' , ' 0 ' ) |
| b2_drq | in bl_drq := ( ' 0 ' , ' 0 ' , ' 0 ' ) |
| b3_drq | in bl_drq := ( ' 0 ' , ' 0 ' , ' 0 ' ) |
| b4_drq | in bl_drq := ( ' 0 ' , ' 0 ' , ' 0 ' ) |
| b5_drq | in bl_drq := ( ' 0 ' , ' 0 ' , ' 0 ' ) |
| b6_drq | in bl_drq := ( ' 0 ' , ' 0 ' , ' 0 ' ) |
| b7_drq | in bl_drq := ( ' 0 ' , ' 0 ' , ' 0 ' ) |
| b8_drq | in bl_drq := ( ' 0 ' , ' 0 ' , ' 0 ' ) |
| b9_drq | in bl_drq := ( ' 0 ' , ' 0 ' , ' 0 ' ) |
| b10_drq | in bl_drq := ( ' 0 ' , ' 0 ' , ' 0 ' ) |
| b11_drq | in bl_drq := ( ' 0 ' , ' 0 ' , ' 0 ' ) |
| b12_drq | in bl_drq := ( ' 0 ' , ' 0 ' , ' 0 ' ) |
| b13_drq | in bl_drq := ( ' 0 ' , ' 0 ' , ' 0 ' ) |
| b14_drq | in bl_drq := ( ' 0 ' , ' 0 ' , ' 0 ' ) |
| b15_drq | in bl_drq := ( ' 0 ' , ' 0 ' , ' 0 ' ) |
| int1 | out std_logic |
| int2 | out std_logic |
| int3 | out std_logic |
| drq0 | out bl_drq |
| drq1 | out bl_drq |
| drq2 | out bl_drq |
| drq3 | out bl_drq |
| reset_out | out std_logic |
| cp0 | out std_logic |
| cp1 | out std_logic |
| goe0 | out std_logic |
| goe1 | out std_logic |
| thclk | out std_logic |
| thdin | out std_logic |
| thrs | out std_logic |
| thld | out std_logic |
| mode0 | out std_logic_vector ( 15 downto 0 ) |
| mode1 | out std_logic_vector ( 15 downto 0 ) |
| synx | out std_logic_vector ( 15 downto 0 ) |
| sel_drq0 | out std_logic_vector ( 6 downto 0 ) |
| sel_drq1 | out std_logic_vector ( 6 downto 0 ) |
| sel_drq2 | out std_logic_vector ( 6 downto 0 ) |
| sel_drq3 | out std_logic_vector ( 6 downto 0 ) |
| b_clk | in std_logic_vector ( 15 downto 0 ) |
| bx_clk | out std_logic |
| b_start | in std_logic_vector ( 15 downto 0 ) |
| bx_start | out std_logic |
| bx_start_a | out std_logic |
| bx_start_sync | out std_logic |
| sn_rdy0 | in std_logic |
| sn_rdy1 | in std_logic |
| sn_start_en | in std_logic |
| sn_sync0 | in std_logic |
| sn_rdy0_out | out std_logic |
| sn_rdy1_out | out std_logic |
| sn_start_en_out | out std_logic |
| sn_sync0_out | out std_logic |
| sn_sync0_in | in std_logic := ' 0 ' |
| sn_rdy0_oe | out std_logic |
| sn_rdy1_oe | out std_logic |
| sn_master | out std_logic |
Подробное описание
См. определение в файле trd_main_v8.vhd строка 239
Объявления и описания членов класса находятся в файле:
- adm/main/trd_main_v8.vhd
