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DS_DMA
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00001 ------------------------------------------------------------------------------- 00002 -- 00003 -- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved. 00004 -- 00005 -- This file contains confidential and proprietary information 00006 -- of Xilinx, Inc. and is protected under U.S. and 00007 -- international copyright and other intellectual property 00008 -- laws. 00009 -- 00010 -- DISCLAIMER 00011 -- This disclaimer is not a license and does not grant any 00012 -- rights to the materials distributed herewith. Except as 00013 -- otherwise provided in a valid license issued to you by 00014 -- Xilinx, and to the maximum extent permitted by applicable 00015 -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 00016 -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 00017 -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 00018 -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 00019 -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 00020 -- (2) Xilinx shall not be liable (whether in contract or tort, 00021 -- including negligence, or under any other theory of 00022 -- liability) for any loss or damage of any kind or nature 00023 -- related to, arising under or in connection with these 00024 -- materials, including for any direct, or any indirect, 00025 -- special, incidental, or consequential loss or damage 00026 -- (including loss of data, profits, goodwill, or any type of 00027 -- loss or damage suffered as a result of any action brought 00028 -- by a third party) even if such damage or loss was 00029 -- reasonably foreseeable or Xilinx had been advised of the 00030 -- possibility of the same. 00031 -- 00032 -- CRITICAL APPLICATIONS 00033 -- Xilinx products are not designed or intended to be fail- 00034 -- safe, or for use in any application requiring fail-safe 00035 -- performance, such as life-support or safety devices or 00036 -- systems, Class III medical devices, nuclear facilities, 00037 -- applications related to the deployment of airbags, or any 00038 -- other applications that could lead to death, personal 00039 -- injury, or severe property or environmental damage 00040 -- (individually and collectively, "Critical 00041 -- Applications"). Customer assumes the sole risk and 00042 -- liability of any use of Xilinx products in Critical 00043 -- Applications, subject only to applicable laws and 00044 -- regulations governing limitations on product liability. 00045 -- 00046 -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 00047 -- PART OF THIS FILE AT ALL TIMES. 00048 -- 00049 ------------------------------------------------------------------------------- 00050 -- Project : Virtex-6 Integrated Block for PCI Express 00051 -- File : axi_basic_top.vhd 00052 -- Version : 2.3 00053 -- 00054 -- Description: 00055 -- TRN/AXI4-S Bridge top level module. Instantiates RX and TX modules. 00056 -- 00057 -- Notes: 00058 -- Optional notes section. 00059 -- 00060 -- Hierarchical: 00061 -- axi_basic_top 00062 -------------------------------------------------------------------------------- 00063 -- Library Declarations 00064 -------------------------------------------------------------------------------- 00065 00066 LIBRARY ieee; 00067 USE ieee.std_logic_1164.all; 00068 USE ieee.std_logic_unsigned.all; 00069 00070 00071 ENTITY axi_basic_top IS 00072 GENERIC ( 00073 C_DATA_WIDTH : INTEGER := 128; -- RX/TX interface data width 00074 C_FAMILY : STRING := "X7"; -- Targeted FPGA family 00075 C_ROOT_PORT : BOOLEAN := FALSE; -- PCIe block is in root port mode 00076 C_PM_PRIORITY : BOOLEAN := FALSE; -- Disable TX packet boundary thrtl 00077 TCQ : INTEGER := 1; -- Clock to Q time 00078 00079 C_REM_WIDTH : INTEGER := 1; -- trem/rrem width 00080 C_STRB_WIDTH : INTEGER := 4 -- TSTRB width 00081 ); 00082 PORT ( 00083 ----------------------------------------------- 00084 -- User Design I/O 00085 ----------------------------------------------- 00086 00087 -- AXI TX 00088 ------------- 00089 s_axis_tx_tdata : IN STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0'); 00090 s_axis_tx_tvalid : IN STD_LOGIC := '0'; 00091 s_axis_tx_tready : OUT STD_LOGIC := '0'; 00092 s_axis_tx_tstrb : IN STD_LOGIC_VECTOR(C_STRB_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0'); 00093 s_axis_tx_tlast : IN STD_LOGIC := '0'; 00094 s_axis_tx_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS=>'0'); 00095 00096 -- AXI RX 00097 ------------- 00098 m_axis_rx_tdata : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0'); 00099 m_axis_rx_tvalid : OUT STD_LOGIC := '0'; 00100 m_axis_rx_tready : IN STD_LOGIC := '0'; 00101 m_axis_rx_tstrb : OUT STD_LOGIC_VECTOR(C_STRB_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0'); 00102 m_axis_rx_tlast : OUT STD_LOGIC := '0'; 00103 m_axis_rx_tuser : OUT STD_LOGIC_VECTOR(21 DOWNTO 0) := (OTHERS=>'0'); 00104 00105 -- User Misc. 00106 ------------- 00107 user_turnoff_ok : IN STD_LOGIC := '0'; 00108 user_tcfg_gnt : IN STD_LOGIC := '0'; 00109 00110 ----------------------------------------------- 00111 -- PCIe Block I/O 00112 ----------------------------------------------- 00113 00114 -- TRN TX 00115 ------------- 00116 trn_td : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0'); 00117 trn_tsof : OUT STD_LOGIC := '0'; 00118 trn_teof : OUT STD_LOGIC := '0'; 00119 trn_tsrc_rdy : OUT STD_LOGIC := '0'; 00120 trn_tdst_rdy : IN STD_LOGIC := '0'; 00121 trn_tsrc_dsc : OUT STD_LOGIC := '0'; 00122 trn_trem : OUT STD_LOGIC_VECTOR(C_REM_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0'); 00123 trn_terrfwd : OUT STD_LOGIC := '0'; 00124 trn_tstr : OUT STD_LOGIC := '0'; 00125 trn_tbuf_av : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS=>'0'); 00126 trn_tecrc_gen : OUT STD_LOGIC := '0'; 00127 00128 -- TRN RX 00129 ------------- 00130 trn_rd : IN STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0'); 00131 trn_rsof : IN STD_LOGIC := '0'; 00132 trn_reof : IN STD_LOGIC := '0'; 00133 trn_rsrc_rdy : IN STD_LOGIC := '0'; 00134 trn_rdst_rdy : OUT STD_LOGIC := '0'; 00135 trn_rsrc_dsc : IN STD_LOGIC := '0'; 00136 trn_rrem : IN STD_LOGIC_VECTOR(C_REM_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0'); 00137 trn_rerrfwd : IN STD_LOGIC := '0'; 00138 trn_rbar_hit : IN STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS=>'0'); 00139 trn_recrc_err : IN STD_LOGIC := '0'; 00140 00141 -- TRN Misc. 00142 ------------- 00143 trn_tcfg_req : IN STD_LOGIC := '0'; 00144 trn_tcfg_gnt : OUT STD_LOGIC := '0'; 00145 trn_lnk_up : IN STD_LOGIC := '0'; 00146 00147 -- 7 Series/Virtex6 PM 00148 ------------- 00149 cfg_pcie_link_state : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS=>'0'); 00150 00151 -- Virtex6 PM 00152 ------------- 00153 cfg_pm_send_pme_to : IN STD_LOGIC := '0'; 00154 cfg_pmcsr_powerstate : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS=>'0'); 00155 trn_rdllp_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=>'0'); 00156 trn_rdllp_src_rdy : IN STD_LOGIC := '0'; 00157 00158 -- Virtex6/Spartan6 PM 00159 ------------- 00160 cfg_to_turnoff : IN STD_LOGIC := '0'; 00161 cfg_turnoff_ok : OUT STD_LOGIC := '0'; 00162 00163 np_counter : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS=>'0'); 00164 user_clk : IN STD_LOGIC := '0'; 00165 user_rst : IN STD_LOGIC := '0' 00166 ); 00167 END axi_basic_top; 00168 00169 00170 ----------------------------------------------- 00171 -- RX Data Pipeline 00172 ----------------------------------------------- 00173 00174 ARCHITECTURE trans OF axi_basic_top IS 00175 COMPONENT axi_basic_rx IS 00176 GENERIC ( 00177 C_DATA_WIDTH : INTEGER := 128; 00178 C_FAMILY : STRING := "X7"; 00179 C_ROOT_PORT : BOOLEAN := FALSE; 00180 C_PM_PRIORITY : BOOLEAN := FALSE; 00181 TCQ : INTEGER := 1; 00182 C_REM_WIDTH : INTEGER := 1; 00183 C_STRB_WIDTH : INTEGER := 4 00184 ); 00185 PORT ( 00186 00187 -- Outgoing AXI TX 00188 ------------- 00189 M_AXIS_RX_TDATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0'); 00190 M_AXIS_RX_TVALID : OUT STD_LOGIC := '0'; 00191 M_AXIS_RX_TREADY : IN STD_LOGIC := '0'; 00192 M_AXIS_RX_TSTRB : OUT STD_LOGIC_VECTOR(C_STRB_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0'); 00193 M_AXIS_RX_TLAST : OUT STD_LOGIC := '0'; 00194 M_AXIS_RX_TUSER : OUT STD_LOGIC_VECTOR(21 DOWNTO 0) := (OTHERS=>'0'); 00195 00196 -- Incoming TRN RX 00197 ------------- 00198 TRN_RD : IN STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0'); 00199 TRN_RSOF : IN STD_LOGIC := '0'; 00200 TRN_REOF : IN STD_LOGIC := '0'; 00201 TRN_RSRC_RDY : IN STD_LOGIC := '0'; 00202 TRN_RDST_RDY : OUT STD_LOGIC := '0'; 00203 TRN_RSRC_DSC : IN STD_LOGIC := '0'; 00204 TRN_RREM : IN STD_LOGIC_VECTOR(C_REM_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0'); 00205 TRN_RERRFWD : IN STD_LOGIC := '0'; 00206 TRN_RBAR_HIT : IN STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS=>'0'); 00207 TRN_RECRC_ERR : IN STD_LOGIC := '0'; 00208 00209 -- System 00210 ------------- 00211 NP_COUNTER : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS=>'0'); 00212 USER_CLK : IN STD_LOGIC := '0'; 00213 USER_RST : IN STD_LOGIC := '0' 00214 ); 00215 END COMPONENT; 00216 00217 ----------------------------------------------- 00218 -- TX Data Pipeline 00219 ----------------------------------------------- 00220 COMPONENT axi_basic_tx IS 00221 GENERIC ( 00222 C_DATA_WIDTH : INTEGER := 128; 00223 C_FAMILY : STRING := "X7"; 00224 C_ROOT_PORT : BOOLEAN := FALSE; 00225 C_PM_PRIORITY : BOOLEAN := FALSE; 00226 TCQ : INTEGER := 1; 00227 00228 C_REM_WIDTH : INTEGER := 1; 00229 C_STRB_WIDTH : INTEGER := 4 00230 ); 00231 PORT ( 00232 -- Incoming AXI RX 00233 ------------- 00234 S_AXIS_TX_TDATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0'); 00235 S_AXIS_TX_TVALID : IN STD_LOGIC := '0'; 00236 S_AXIS_TX_TREADY : OUT STD_LOGIC := '0'; 00237 S_AXIS_TX_TSTRB : IN STD_LOGIC_VECTOR(C_STRB_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0'); 00238 S_AXIS_TX_TLAST : IN STD_LOGIC := '0'; 00239 S_AXIS_TX_TUSER : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS=>'0'); 00240 00241 -- User Misc. 00242 ------------- 00243 USER_TURNOFF_OK : IN STD_LOGIC := '0'; 00244 USER_TCFG_GNT : IN STD_LOGIC := '0'; 00245 00246 -- Outgoing TRN TX 00247 ------------- 00248 TRN_TD : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0'); 00249 TRN_TSOF : OUT STD_LOGIC := '0'; 00250 TRN_TEOF : OUT STD_LOGIC := '0'; 00251 TRN_TSRC_RDY : OUT STD_LOGIC := '0'; 00252 TRN_TDST_RDY : IN STD_LOGIC := '0'; 00253 TRN_TSRC_DSC : OUT STD_LOGIC; 00254 TRN_TREM : OUT STD_LOGIC_VECTOR(C_REM_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0'); 00255 TRN_TERRFWD : OUT STD_LOGIC := '0'; 00256 TRN_TSTR : OUT STD_LOGIC := '0'; 00257 TRN_TBUF_AV : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS=>'0'); 00258 TRN_TECRC_GEN : OUT STD_LOGIC := '0'; 00259 00260 -- TRN Misc. 00261 ------------- 00262 TRN_TCFG_REQ : IN STD_LOGIC := '0'; 00263 TRN_TCFG_GNT : OUT STD_LOGIC := '0'; 00264 TRN_LNK_UP : IN STD_LOGIC := '0'; 00265 00266 -- 7 Series/Virtex6 PM 00267 ------------- 00268 CFG_PCIE_LINK_STATE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS=>'0'); 00269 00270 -- Virtex6 PM 00271 ------------- 00272 CFG_PM_SEND_PME_TO : IN STD_LOGIC := '0'; 00273 CFG_PMCSR_POWERSTATE : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS=>'0'); 00274 TRN_RDLLP_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=>'0'); 00275 TRN_RDLLP_SRC_RDY : IN STD_LOGIC; 00276 00277 -- Spartan6 PM 00278 ------------- 00279 CFG_TO_TURNOFF : IN STD_LOGIC := '0'; 00280 CFG_TURNOFF_OK : OUT STD_LOGIC := '0'; 00281 00282 -- System 00283 ------------- 00284 USER_CLK : IN STD_LOGIC := '0'; 00285 USER_RST : IN STD_LOGIC := '0' 00286 ); 00287 END COMPONENT axi_basic_tx; 00288 00289 00290 BEGIN 00291 00292 rx_inst : axi_basic_rx 00293 GENERIC MAP ( 00294 C_DATA_WIDTH => C_DATA_WIDTH, 00295 TCQ => TCQ, 00296 C_FAMILY => C_FAMILY, 00297 C_REM_WIDTH => C_REM_WIDTH, 00298 C_STRB_WIDTH => C_STRB_WIDTH 00299 ) 00300 PORT MAP ( 00301 00302 M_AXIS_RX_TDATA => m_axis_rx_tdata, 00303 M_AXIS_RX_TVALID => m_axis_rx_tvalid, 00304 M_AXIS_RX_TREADY => m_axis_rx_tready, 00305 M_AXIS_RX_TSTRB => m_axis_rx_tstrb, 00306 M_AXIS_RX_TLAST => m_axis_rx_tlast, 00307 M_AXIS_RX_TUSER => m_axis_rx_tuser, 00308 00309 TRN_RD => trn_rd, 00310 TRN_RSOF => trn_rsof, 00311 TRN_REOF => trn_reof, 00312 TRN_RSRC_RDY => trn_rsrc_rdy, 00313 TRN_RDST_RDY => trn_rdst_rdy, 00314 TRN_RSRC_DSC => trn_rsrc_dsc, 00315 TRN_RREM => trn_rrem, 00316 TRN_RERRFWD => trn_rerrfwd, 00317 TRN_RBAR_HIT => trn_rbar_hit, 00318 TRN_RECRC_ERR => trn_recrc_err, 00319 00320 NP_COUNTER => np_counter, 00321 USER_CLK => user_clk, 00322 USER_RST => user_rst 00323 ); 00324 00325 tx_inst : axi_basic_tx 00326 GENERIC MAP ( 00327 C_DATA_WIDTH => C_DATA_WIDTH, 00328 C_FAMILY => C_FAMILY, 00329 C_ROOT_PORT => C_ROOT_PORT, 00330 C_PM_PRIORITY => C_PM_PRIORITY, 00331 TCQ => TCQ, 00332 C_REM_WIDTH => C_REM_WIDTH, 00333 C_STRB_WIDTH => C_STRB_WIDTH 00334 ) 00335 PORT MAP ( 00336 00337 S_AXIS_TX_TDATA => s_axis_tx_tdata, 00338 S_AXIS_TX_TVALID => s_axis_tx_tvalid, 00339 S_AXIS_TX_TREADY => s_axis_tx_tready, 00340 S_AXIS_TX_TSTRB => s_axis_tx_tstrb, 00341 S_AXIS_TX_TLAST => s_axis_tx_tlast, 00342 S_AXIS_TX_TUSER => s_axis_tx_tuser, 00343 00344 USER_TURNOFF_OK => user_turnoff_ok, 00345 USER_TCFG_GNT => user_tcfg_gnt, 00346 00347 TRN_TD => trn_td, 00348 TRN_TSOF => trn_tsof, 00349 TRN_TEOF => trn_teof, 00350 TRN_TSRC_RDY => trn_tsrc_rdy, 00351 TRN_TDST_RDY => trn_tdst_rdy, 00352 TRN_TSRC_DSC => trn_tsrc_dsc, 00353 TRN_TREM => trn_trem, 00354 TRN_TERRFWD => trn_terrfwd, 00355 TRN_TSTR => trn_tstr, 00356 TRN_TBUF_AV => trn_tbuf_av, 00357 TRN_TECRC_GEN => trn_tecrc_gen, 00358 00359 TRN_TCFG_REQ => trn_tcfg_req, 00360 TRN_TCFG_GNT => trn_tcfg_gnt, 00361 TRN_LNK_UP => trn_lnk_up, 00362 00363 CFG_PCIE_LINK_STATE => cfg_pcie_link_state , 00364 00365 CFG_PM_SEND_PME_TO => cfg_pm_send_pme_to, 00366 CFG_PMCSR_POWERSTATe => cfg_pmcsr_powerstate, 00367 TRN_RDLLP_DATA => trn_rdllp_data, 00368 TRN_RDLLP_SRC_RDY => trn_rdllp_src_rdy, 00369 00370 CFG_TO_TURNOFF => cfg_to_turnoff, 00371 CFG_TURNOFF_OK => cfg_turnoff_ok, 00372 00373 USER_CLK => user_clk, 00374 USER_RST => user_rst 00375 ); 00376 00377 END trans; 00378 00379
1.7.4