DS_DMA
Generics | Ports | Libraries | Packages
axi_basic_tx Entity Reference
Граф наследования:axi_basic_tx:
trans axi_basic_tx_pipeline axi_basic_tx_thrtl_ctl trans trans trans axi_basic_top v6_pcie v6_pcie cl_v6pcie_m1 cl_v6pcie_x4 pcie_core64_m4 pcie_core64_m4 pcie_core64_m4_pkg pcie_core64_m5 pcie_core64_m5 pcie_core64_m5_pkg

Полный список членов класса



Architectures

trans  Architecture

Libraries

ieee 

Packages

std_logic_1164 
std_logic_unsigned 

Generics

C_DATA_WIDTH  integer := 128
C_FAMILY  string := " x7 "
C_ROOT_PORT  boolean := false
C_PM_PRIORITY  boolean := false
TCQ  integer := 1
C_REM_WIDTH  integer := 1
C_STRB_WIDTH  integer := 4

Ports

S_AXIS_TX_TDATA   in std_logic_vector ( c_data_width- 1 downto 0 )
S_AXIS_TX_TVALID   in std_logic
S_AXIS_TX_TREADY   out std_logic
S_AXIS_TX_TSTRB   in std_logic_vector ( c_strb_width- 1 downto 0 )
S_AXIS_TX_TLAST   in std_logic
S_AXIS_TX_TUSER   in std_logic_vector ( 3 downto 0 )
USER_TURNOFF_OK   in std_logic
USER_TCFG_GNT   in std_logic
TRN_TD   out std_logic_vector ( c_data_width- 1 downto 0 )
TRN_TSOF   out std_logic
TRN_TEOF   out std_logic
TRN_TSRC_RDY   out std_logic
TRN_TDST_RDY   in std_logic
TRN_TSRC_DSC   out std_logic
TRN_TREM   out std_logic_vector ( c_rem_width- 1 downto 0 )
TRN_TERRFWD   out std_logic
TRN_TSTR   out std_logic
TRN_TBUF_AV   in std_logic_vector ( 5 downto 0 )
TRN_TECRC_GEN   out std_logic
TRN_TCFG_REQ   in std_logic
TRN_TCFG_GNT   out std_logic
TRN_LNK_UP   in std_logic
CFG_PCIE_LINK_STATE   in std_logic_vector ( 2 downto 0 )
CFG_PM_SEND_PME_TO   in std_logic
CFG_PMCSR_POWERSTATE   in std_logic_vector ( 1 downto 0 )
TRN_RDLLP_DATA   in std_logic_vector ( 31 downto 0 )
TRN_RDLLP_SRC_RDY   in std_logic
CFG_TO_TURNOFF   in std_logic
CFG_TURNOFF_OK   out std_logic
USER_CLK   in std_logic
USER_RST   in std_logic

Подробное описание

См. определение в файле axi_basic_tx.vhd строка 74


Объявления и описания членов класса находятся в файле: