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DS_DMA
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00001 ------------------------------------------------------------------------------- 00002 -- 00003 -- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved. 00004 -- 00005 -- This file contains confidential and proprietary information 00006 -- of Xilinx, Inc. and is protected under U.S. and 00007 -- international copyright and other intellectual property 00008 -- laws. 00009 -- 00010 -- DISCLAIMER 00011 -- This disclaimer is not a license and does not grant any 00012 -- rights to the materials distributed herewith. Except as 00013 -- otherwise provided in a valid license issued to you by 00014 -- Xilinx, and to the maximum extent permitted by applicable 00015 -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 00016 -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 00017 -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 00018 -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 00019 -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 00020 -- (2) Xilinx shall not be liable (whether in contract or tort, 00021 -- including negligence, or under any other theory of 00022 -- liability) for any loss or damage of any kind or nature 00023 -- related to, arising under or in connection with these 00024 -- materials, including for any direct, or any indirect, 00025 -- special, incidental, or consequential loss or damage 00026 -- (including loss of data, profits, goodwill, or any type of 00027 -- loss or damage suffered as a result of any action brought 00028 -- by a third party) even if such damage or loss was 00029 -- reasonably foreseeable or Xilinx had been advised of the 00030 -- possibility of the same. 00031 -- 00032 -- CRITICAL APPLICATIONS 00033 -- Xilinx products are not designed or intended to be fail- 00034 -- safe, or for use in any application requiring fail-safe 00035 -- performance, such as life-support or safety devices or 00036 -- systems, Class III medical devices, nuclear facilities, 00037 -- applications related to the deployment of airbags, or any 00038 -- other applications that could lead to death, personal 00039 -- injury, or severe property or environmental damage 00040 -- (individually and collectively, "Critical 00041 -- Applications"). Customer assumes the sole risk and 00042 -- liability of any use of Xilinx products in Critical 00043 -- Applications, subject only to applicable laws and 00044 -- regulations governing limitations on product liability. 00045 -- 00046 -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 00047 -- PART OF THIS FILE AT ALL TIMES. 00048 -- 00049 ------------------------------------------------------------------------------- 00050 -- Project : Virtex-6 Integrated Block for PCI Express 00051 -- File : axi_basic_tx.vhd 00052 -- Version : 2.3 00053 -- 00054 -- Description: 00055 --AXI to TRN TX module. Instantiates pipeline and throttle control TX 00056 -- submodules. 00057 -- 00058 -- Notes: 00059 -- Optional notes section. 00060 -- 00061 -- Hierarchical: 00062 -- axi_basic_top 00063 -- axi_basic_tx 00064 -- 00065 -------------------------------------------------------------------------------- 00066 -- Library Declarations 00067 -------------------------------------------------------------------------------- 00068 00069 LIBRARY ieee; 00070 USE ieee.std_logic_1164.all; 00071 USE ieee.std_logic_unsigned.all; 00072 00073 00074 ENTITY axi_basic_tx IS 00075 GENERIC ( 00076 C_DATA_WIDTH : INTEGER := 128; -- RX/TX interface data width 00077 C_FAMILY : STRING := "X7"; -- Targeted FPGA family 00078 C_ROOT_PORT : BOOLEAN := FALSE; -- PCIe block is in root port mode 00079 C_PM_PRIORITY : BOOLEAN := FALSE; -- Disable TX packet boundary thrtl 00080 TCQ : INTEGER := 1; -- Clock to Q time 00081 00082 C_REM_WIDTH : INTEGER := 1; -- trem/rrem width 00083 C_STRB_WIDTH : INTEGER := 4 -- TSTRB width 00084 ); 00085 PORT ( 00086 00087 ----------------------------------------------- 00088 -- User Design I/O 00089 ----------------------------------------------- 00090 00091 -- AXI TX 00092 ------------- 00093 S_AXIS_TX_TDATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0); 00094 S_AXIS_TX_TVALID : IN STD_LOGIC; 00095 S_AXIS_TX_TREADY : OUT STD_LOGIC; 00096 S_AXIS_TX_TSTRB : IN STD_LOGIC_VECTOR(C_STRB_WIDTH - 1 DOWNTO 0); 00097 S_AXIS_TX_TLAST : IN STD_LOGIC; 00098 S_AXIS_TX_TUSER : IN STD_LOGIC_VECTOR(3 DOWNTO 0); 00099 00100 -- User Misc. 00101 ------------- 00102 USER_TURNOFF_OK : IN STD_LOGIC; 00103 USER_TCFG_GNT : IN STD_LOGIC; 00104 00105 ----------------------------------------------- 00106 -- PCIe Block I/O 00107 ----------------------------------------------- 00108 00109 -- TRN TX 00110 ------------- 00111 TRN_TD : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0); 00112 TRN_TSOF : OUT STD_LOGIC; 00113 TRN_TEOF : OUT STD_LOGIC; 00114 TRN_TSRC_RDY : OUT STD_LOGIC; 00115 TRN_TDST_RDY : IN STD_LOGIC; 00116 TRN_TSRC_DSC : OUT STD_LOGIC; 00117 TRN_TREM : OUT STD_LOGIC_VECTOR(C_REM_WIDTH - 1 DOWNTO 0); 00118 TRN_TERRFWD : OUT STD_LOGIC; 00119 TRN_TSTR : OUT STD_LOGIC; 00120 TRN_TBUF_AV : IN STD_LOGIC_VECTOR(5 DOWNTO 0); 00121 TRN_TECRC_GEN : OUT STD_LOGIC; 00122 00123 -- TRN Misc. 00124 ----------- 00125 TRN_TCFG_REQ : IN STD_LOGIC; 00126 TRN_TCFG_GNT : OUT STD_LOGIC; 00127 TRN_LNK_UP : IN STD_LOGIC; 00128 00129 -- 7 Series/Virtex6 PM 00130 ----------- 00131 CFG_PCIE_LINK_STATE : IN STD_LOGIC_VECTOR(2 DOWNTO 0); 00132 00133 -- Virtex6 PM 00134 ----------- 00135 CFG_PM_SEND_PME_TO : IN STD_LOGIC; 00136 CFG_PMCSR_POWERSTATE : IN STD_LOGIC_VECTOR(1 DOWNTO 0); 00137 TRN_RDLLP_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 00138 TRN_RDLLP_SRC_RDY : IN STD_LOGIC; 00139 00140 -- Virtex6/Spartan6 PM 00141 ----------- 00142 CFG_TO_TURNOFF : IN STD_LOGIC; 00143 CFG_TURNOFF_OK : OUT STD_LOGIC; 00144 00145 -- System 00146 ----------- 00147 USER_CLK : IN STD_LOGIC; 00148 USER_RST : IN STD_LOGIC 00149 ); 00150 END axi_basic_tx; 00151 00152 ARCHITECTURE trans OF axi_basic_tx IS 00153 00154 SIGNAL tready_thrtl : STD_LOGIC; 00155 00156 -- Declare intermediate signals for referenced outputs 00157 SIGNAL s_axis_tx_tready_xhdl1 : STD_LOGIC; 00158 SIGNAL trn_td_xhdl3 : STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0); 00159 SIGNAL trn_tsof_xhdl8 : STD_LOGIC; 00160 SIGNAL trn_teof_xhdl5 : STD_LOGIC; 00161 SIGNAL trn_tsrc_rdy_xhdl10 : STD_LOGIC; 00162 SIGNAL trn_tsrc_dsc_xhdl9 : STD_LOGIC; 00163 SIGNAL trn_trem_xhdl7 : STD_LOGIC_VECTOR(C_REM_WIDTH - 1 DOWNTO 0); 00164 SIGNAL trn_terrfwd_xhdl6 : STD_LOGIC; 00165 SIGNAL trn_tstr_xhdl11 : STD_LOGIC; 00166 SIGNAL trn_tecrc_gen_xhdl4 : STD_LOGIC; 00167 SIGNAL trn_tcfg_gnt_xhdl2 : STD_LOGIC; 00168 SIGNAL cfg_turnoff_ok_xhdl0 : STD_LOGIC; 00169 00170 COMPONENT axi_basic_tx_thrtl_ctl IS 00171 GENERIC ( 00172 C_DATA_WIDTH : INTEGER := 128; 00173 C_FAMILY : STRING := "X7"; 00174 C_ROOT_PORT : BOOLEAN := FALSE; 00175 TCQ : INTEGER := 1 00176 ); 00177 PORT ( 00178 S_AXIS_TX_TDATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0); 00179 S_AXIS_TX_TVALID : IN STD_LOGIC; 00180 S_AXIS_TX_TUSER : IN STD_LOGIC_VECTOR(3 DOWNTO 0); 00181 S_AXIS_TX_TLAST : IN STD_LOGIC; 00182 USER_TURNOFF_OK : IN STD_LOGIC; 00183 USER_TCFG_GNT : IN STD_LOGIC; 00184 TRN_TBUF_AV : IN STD_LOGIC_VECTOR(5 DOWNTO 0); 00185 TRN_TDST_RDY : IN STD_LOGIC; 00186 TRN_TCFG_REQ : IN STD_LOGIC; 00187 TRN_TCFG_GNT : OUT STD_LOGIC; 00188 TRN_LNK_UP : IN STD_LOGIC; 00189 CFG_PCIE_LINK_STATE : IN STD_LOGIC_VECTOR(2 DOWNTO 0); 00190 CFG_PM_SEND_PME_TO : IN STD_LOGIC; 00191 CFG_PMCSR_POWERSTATE : IN STD_LOGIC_VECTOR(1 DOWNTO 0); 00192 TRN_RDLLP_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 00193 TRN_RDLLP_SRC_RDY : IN STD_LOGIC; 00194 CFG_TO_TURNOFF : IN STD_LOGIC; 00195 CFG_TURNOFF_OK : OUT STD_LOGIC; 00196 TREADY_THRTL : OUT STD_LOGIC; 00197 USER_CLK : IN STD_LOGIC; 00198 USER_RST : IN STD_LOGIC 00199 ); 00200 END COMPONENT axi_basic_tx_thrtl_ctl; 00201 00202 ----------------------------------------------- 00203 -- TX Data Pipeline 00204 ----------------------------------------------- 00205 COMPONENT axi_basic_tx_pipeline IS 00206 GENERIC ( 00207 C_DATA_WIDTH : INTEGER := 128; 00208 C_PM_PRIORITY : BOOLEAN := FALSE; 00209 TCQ : INTEGER := 1; 00210 00211 C_REM_WIDTH : INTEGER := 1; 00212 C_STRB_WIDTH : INTEGER := 8 00213 ); 00214 PORT ( 00215 00216 -- Incoming AXI RX 00217 ------------- 00218 S_AXIS_TX_TDATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0); 00219 S_AXIS_TX_TVALID : IN STD_LOGIC; 00220 S_AXIS_TX_TREADY : OUT STD_LOGIC; 00221 S_AXIS_TX_TSTRB : IN STD_LOGIC_VECTOR(C_STRB_WIDTH - 1 DOWNTO 0); 00222 S_AXIS_TX_TLAST : IN STD_LOGIC; 00223 S_AXIS_TX_TUSER : IN STD_LOGIC_VECTOR(3 DOWNTO 0); 00224 00225 -- Outgoing TRN TX 00226 ------------- 00227 TRN_TD : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0); 00228 TRN_TSOF : OUT STD_LOGIC; 00229 TRN_TEOF : OUT STD_LOGIC; 00230 TRN_TSRC_RDY : OUT STD_LOGIC; 00231 TRN_TDST_RDY : IN STD_LOGIC; 00232 TRN_TSRC_DSC : OUT STD_LOGIC; 00233 TRN_TREM : OUT STD_LOGIC_VECTOR(C_REM_WIDTH - 1 DOWNTO 0); 00234 TRN_TERRFWD : OUT STD_LOGIC; 00235 TRN_TSTR : OUT STD_LOGIC; 00236 TRN_TECRC_GEN : OUT STD_LOGIC; 00237 TRN_LNK_UP : IN STD_LOGIC; 00238 00239 -- System 00240 ------------- 00241 TREADY_THRTL : IN STD_LOGIC; 00242 USER_CLK : IN STD_LOGIC; 00243 USER_RST : IN STD_LOGIC 00244 ); 00245 END COMPONENT axi_basic_tx_pipeline; 00246 00247 BEGIN 00248 -- Drive referenced outputs 00249 S_AXIS_TX_TREADY <= s_axis_tx_tready_xhdl1; 00250 TRN_TD <= trn_td_xhdl3; 00251 TRN_TSOF <= trn_tsof_xhdl8; 00252 TRN_TEOF <= trn_teof_xhdl5; 00253 TRN_TSRC_RDY <= trn_tsrc_rdy_xhdl10; 00254 TRN_TSRC_DSC <= trn_tsrc_dsc_xhdl9; 00255 TRN_TREM <= trn_trem_xhdl7; 00256 TRN_TERRFWD <= trn_terrfwd_xhdl6; 00257 TRN_TSTR <= trn_tstr_xhdl11; 00258 TRN_TECRC_GEN <= trn_tecrc_gen_xhdl4; 00259 TRN_TCFG_GNT <= trn_tcfg_gnt_xhdl2; 00260 CFG_TURNOFF_OK <= cfg_turnoff_ok_xhdl0; 00261 00262 00263 00264 tx_pipeline_inst : axi_basic_tx_pipeline 00265 GENERIC MAP ( 00266 C_DATA_WIDTH => C_DATA_WIDTH, 00267 C_PM_PRIORITY => C_PM_PRIORITY, 00268 TCQ => TCQ, 00269 C_REM_WIDTH => C_REM_WIDTH, 00270 C_STRB_WIDTH => C_STRB_WIDTH 00271 ) 00272 PORT MAP ( 00273 00274 S_AXIS_TX_TDATA => S_AXIS_TX_TDATA, 00275 S_AXIS_TX_TREADY => s_axis_tx_tready_xhdl1, 00276 S_AXIS_TX_TVALID => S_AXIS_TX_TVALID, 00277 S_AXIS_TX_TSTRB => S_AXIS_TX_TSTRB, 00278 S_AXIS_TX_TLAST => S_AXIS_TX_TLAST, 00279 S_AXIS_TX_TUSER => S_AXIS_TX_TUSER, 00280 00281 TRN_TD => trn_td_xhdl3, 00282 TRN_TSOF => trn_tsof_xhdl8, 00283 TRN_TEOF => trn_teof_xhdl5, 00284 TRN_TSRC_RDY => trn_tsrc_rdy_xhdl10, 00285 TRN_TDST_RDY => TRN_TDST_RDY, 00286 TRN_TSRC_DSC => trn_tsrc_dsc_xhdl9, 00287 TRN_TREM => trn_trem_xhdl7, 00288 TRN_TERRFWD => trn_terrfwd_xhdl6, 00289 TRN_TSTR => trn_tstr_xhdl11, 00290 TRN_TECRC_GEN => trn_tecrc_gen_xhdl4, 00291 TRN_LNK_UP => trn_lnk_up, 00292 00293 TREADY_THRTL => TREADY_THRTL, 00294 USER_CLK => USER_CLK, 00295 USER_RST => USER_RST 00296 ); 00297 00298 ------------------------------------------------- 00299 -- TX Throttle Controller 00300 ------------------------------------------------- 00301 xhdl12 : IF (NOT(C_PM_PRIORITY)) GENERATE 00302 tx_thrl_ctl_inst : axi_basic_tx_thrtl_ctl 00303 GENERIC MAP ( 00304 C_DATA_WIDTH => C_DATA_WIDTH, 00305 C_FAMILY => C_FAMILY, 00306 C_ROOT_PORT => C_ROOT_PORT, 00307 TCQ => TCQ 00308 ) 00309 PORT MAP ( 00310 -- Outgoing AXI TX 00311 ------------- 00312 S_AXIS_TX_TDATA => S_AXIS_TX_TDATA, 00313 S_AXIS_TX_TVALID => S_AXIS_TX_TVALID, 00314 S_AXIS_TX_TUSER => S_AXIS_TX_TUSER, 00315 S_AXIS_TX_TLAST => S_AXIS_TX_TLAST, 00316 00317 -- User Misc. 00318 ------------- 00319 USER_TURNOFF_OK => USER_TURNOFF_OK, 00320 USER_TCFG_GNT => USER_TCFG_GNT, 00321 00322 -- Incoming TRN RX 00323 ------------- 00324 TRN_TBUF_AV => TRN_TBUF_AV, 00325 TRN_TDST_RDY => TRN_TDST_RDY, 00326 00327 -- TRN Misc. 00328 ------------- 00329 TRN_TCFG_REQ => TRN_TCFG_REQ, 00330 TRN_TCFG_GNT => trn_tcfg_gnt_xhdl2, 00331 TRN_LNK_UP => trn_lnk_up, 00332 00333 -- 7 Seriesq/Virtex6 PM 00334 ------------- 00335 CFG_PCIE_LINK_STATE => CFG_PCIE_LINK_STATE, 00336 00337 -- Virtex6 PM 00338 ------------- 00339 CFG_PM_SEND_PME_TO => CFG_PM_SEND_PME_TO, 00340 CFG_PMCSR_POWERSTATE => CFG_PMCSR_POWERSTATE, 00341 TRN_RDLLP_DATA => TRN_RDLLP_DATA, 00342 TRN_RDLLP_SRC_RDY => TRN_RDLLP_SRC_RDY, 00343 00344 -- Spartan6 PM 00345 ------------- 00346 CFG_TO_TURNOFF => CFG_TO_TURNOFF, 00347 CFG_TURNOFF_OK => cfg_turnoff_ok_xhdl0, 00348 00349 -- System 00350 ------------- 00351 TREADY_THRTL => TREADY_THRTL, 00352 USER_CLK => USER_CLK, 00353 USER_RST => USER_RST 00354 ); 00355 END GENERATE; 00356 xhdl13 : IF (C_PM_PRIORITY) GENERATE 00357 TREADY_THRTL <= '0'; 00358 cfg_turnoff_ok_xhdl0 <= USER_TURNOFF_OK; 00359 trn_tcfg_gnt_xhdl2 <= USER_TCFG_GNT; 00360 END GENERATE; 00361 END trans;
1.7.4