axi_basic_tx_pipeline Entity Reference

Граф наследования:axi_basic_tx_pipeline:

Полный список членов класса

Architectures
trans	Architecture
Libraries
ieee
Packages
std_logic_1164
std_logic_unsigned
Generics
C_DATA_WIDTH	integer := 128
C_PM_PRIORITY	boolean := false
TCQ	integer := 1
C_REM_WIDTH	integer := 1
C_STRB_WIDTH	integer := 8
Ports
S_AXIS_TX_TDATA	in std_logic_vector ( c_data_width- 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS_TX_TVALID	in std_logic := ' 0 '
S_AXIS_TX_TREADY	out std_logic := ' 0 '
S_AXIS_TX_TSTRB	in std_logic_vector ( c_strb_width- 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS_TX_TLAST	in std_logic := ' 0 '
S_AXIS_TX_TUSER	in std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
TRN_TD	out std_logic_vector ( c_data_width- 1 downto 0 ) := ( others = > ' 0 ' )
TRN_TSOF	out std_logic := ' 0 '
TRN_TEOF	out std_logic := ' 0 '
TRN_TSRC_RDY	out std_logic := ' 0 '
TRN_TDST_RDY	in std_logic := ' 0 '
TRN_TSRC_DSC	out std_logic := ' 0 '
TRN_TREM	out std_logic_vector ( c_rem_width- 1 downto 0 ) := ( others = > ' 0 ' )
TRN_TERRFWD	out std_logic := ' 0 '
TRN_TSTR	out std_logic := ' 0 '
TRN_TECRC_GEN	out std_logic := ' 0 '
TRN_LNK_UP	in std_logic := ' 0 '
TREADY_THRTL	in std_logic := ' 0 '
USER_CLK	in std_logic := ' 0 '
USER_RST	in std_logic := ' 0 '

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Подробное описание

См. определение в файле axi_basic_tx_pipeline.vhd строка 74

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Объявления и описания членов класса находятся в файле:

• pcie_src/pcie_core64_m1/source_virtex6/axi_basic_tx_pipeline.vhd