DS_DMA
|
Processes | |
pr_rx_first | ( clk ) |
pr_fifo0_wr | ( clk ) |
pr_fifo1_wr | ( clk ) |
pr_stp | ( clk ) |
pr_stf | ( clk ) |
pr_adr_cnt | ( clk ) |
Components | |
ctrl_fifo64x70st | <Entity ctrl_fifo64x70st> |
Types | |
stp_type | ( s0 , s1 , s2 , s3 , s31 , s32 , s4 , s5 ) |
stf_type | ( s0 , s1 , s2 , s3 , s4 , s5 , s6 ) |
Signals | |
rstpz | std_logic |
stp | stp_type |
stf | stf_type |
trn_rdst_rdy_n | std_logic |
trn_rnp_ok_n | std_logic |
trn_rcpl_streaming_n | std_logic |
tlp_dw0 | std_logic_vector ( 31 downto 0 ) |
tlp_dw1 | std_logic_vector ( 31 downto 0 ) |
tlp_dw2 | std_logic_vector ( 31 downto 0 ) |
tlp_dw3 | std_logic_vector ( 31 downto 0 ) |
trn_data | std_logic_vector ( 63 downto 0 ) |
trn_data_we | std_logic |
tlp_cnt | std_logic_vector ( 5 downto 0 ) |
request_reg_wr | std_logic |
request_reg_rd | std_logic |
tlp_complete | std_logic |
bar | std_logic_vector ( 1 downto 0 ) |
fifo_wr | std_logic |
fifo_wr_z | std_logic |
fifo_din | std_logic_vector ( 69 downto 0 ) |
fifo0_wr | std_logic |
fifo0_wr_en | std_logic |
fifo0_wr_en_z | std_logic |
fifo0_rd | std_logic |
fifo0_full | std_logic |
fifo0_empty | std_logic |
fifo0_valid | std_logic |
fifo0_paf | std_logic |
fifo0_pae | std_logic |
fifo0_dout | std_logic_vector ( 69 downto 0 ) |
fifo1_wr | std_logic |
fifo1_wr_en | std_logic |
fifo1_wr_en_z | std_logic |
fifo1_rd | std_logic |
fifo1_rd_x | std_logic |
fifo1_full | std_logic |
fifo1_empty | std_logic |
fifo1_valid | std_logic |
fifo1_paf | std_logic |
fifo1_pae | std_logic |
fifo1_dout | std_logic_vector ( 69 downto 0 ) |
data_rx | std_logic_vector ( 63 downto 0 ) |
data_rx_we | std_logic |
data_rx_we_en | std_logic |
data_lrx | std_logic_vector ( 31 downto 0 ) |
data_hrx | std_logic_vector ( 31 downto 0 ) |
tlp_cp_dw0 | std_logic_vector ( 31 downto 0 ) |
tlp_cp_dw1 | std_logic_vector ( 31 downto 0 ) |
tlp_cp_dw2 | std_logic_vector ( 31 downto 0 ) |
tlp_cp_dw3 | std_logic_vector ( 31 downto 0 ) |
adr_rx | std_logic_vector ( 8 downto 0 ) |
adr_cnt | std_logic_vector ( 3 downto 0 ) |
axis_rx_tready | std_logic |
rx_first | std_logic |
Component Instantiations | |
fifo0_reg | ctrl_fifo64x70st <Entity ctrl_fifo64x70st> |
fifo1_cmpl | ctrl_fifo64x70st <Entity ctrl_fifo64x70st> |
См. определение в файле core64_rx_engine_m2.vhd строка 84