|
DS_DMA
|
Architectures | |
| ctrl_dma_adr | Architecture |
Libraries | |
| ieee | |
| unisim | |
Packages | |
| std_logic_1164 | |
| std_logic_arith | |
| std_logic_unsigned | |
| vcomponents | |
Generics | |
| is_dsp48 | in integer := 1 |
Ports | |
| clk | in std_logic |
| dma_chn | in std_logic |
| reg0 | in std_logic_vector ( 2 downto 0 ) |
| reg41_wr | in std_logic |
| dsc_adr | in std_logic_vector ( 23 downto 0 ) |
| dsc_adr_h | in std_logic_vector ( 7 downto 0 ) |
| dsc_size | in std_logic_vector ( 23 downto 0 ) |
| pci_adr | out std_logic_vector ( 39 downto 0 ) |
| pci_size_z | out std_logic |
| pci_rw | out std_logic |
См. определение в файле ctrl_dma_adr.vhd строка 75
1.7.4