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DS_DMA
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Architectures | |
| ctrl_ext_descriptor | Architecture |
Libraries | |
| ieee | |
| unisim | |
Packages | |
| std_logic_1164 | |
| std_logic_arith | |
| std_logic_unsigned | |
| vcomponents | |
Generics | |
| is_dsp48 | in integer := 1 |
Ports | |
| reset | in std_logic |
| clk | in std_logic |
| data_in | in std_logic_vector ( 31 downto 0 ) |
| pci_adr_we | in std_logic |
| pci_adr_h_we | in std_logic |
| dma_chn | in std_logic |
| dsc_correct | out std_logic |
| dsc_cmd | out std_logic_vector ( 7 downto 0 ) |
| dsc_change_adr | in std_logic |
| dsc_change_mode | in std_logic |
| dsc_load_en | in std_logic |
| ram0_wr | in std_logic |
| dma_wraddr | in std_logic_vector ( 11 downto 0 ) |
| dma_wrdata | in std_logic_vector ( 63 downto 0 ) |
| dsc_adr_h | out std_logic_vector ( 7 downto 0 ) |
| dsc_adr | out std_logic_vector ( 23 downto 0 ) |
| dsc_size | out std_logic_vector ( 23 downto 0 ) |
| test | out std_logic_vector ( 3 downto 0 ) |
См. определение в файле ctrl_ext_descriptor.vhd строка 110
1.7.4